Chain logic scheme for programmed logic array

Details Chain logic scheme for programmed logic array Chain logic scheme for programmed logic array

1984-03-26

1987-05-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 364488, H03K 19096, H03K 19173, G06F 738

Patent

active

046688803

ABSTRACT:
Additional data processing capability can be added to a programmed logic array (PLA), having an AND plane and an OR plane connected serially between an input register and an output register, by inserting a multistage domino CMOS logic network between the OR plane and the output register. The OR plane is an array of single-stage domino CMOS logic and is timed so that it precharges simultaneously with the multistage network. Without prolonging the individual phase durations or adding any registers, the added domino logic network can have a propagation delay time corresponding to more than one phase of the PLA, and hence the network can have correspondingly more stages and more added data processing capability.

REFERENCES:
patent: 4399516 (1983-08-01), Blahut et al.
patent: 4488230 (1984-12-01), Harrison
R. J. Delahanty, "PLA with Internally Ored Functions," IBM Technical Disclosure Bulletin, vol. 23, No. 8 (Jan. 1981), pp. 3759-3760.
R. H. Krambeck et al., "High-Speed Compact Circuits With CMOS," IEEEE Journal of Solid-State Circuits, vol. SC-17, No. 3, Jun. 1982, pp. 614-619.
M. Shoji, "Electrical Design of BELLMAC-32A Microprocessor," IEEE International Conference on Circuits and Computers-ICCC 82, New York, New York, Sep. 28-Oct. 1, 1982, pp. 112-115.
I.B.M. Tech. Disc. Bul., "PLA with Internally ORED Logic.
I.E.E.E. Journal of Solid-State Circuits, R. H. Krambeck.

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