Chain gate MOS structure

Details Chain gate MOS structure Chain gate MOS structure

2000-11-16

2002-06-11

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S210000, C257S342000, C257S401000, C257S758000, C257S773000

Reexamination Certificate

active

06404030

ABSTRACT:

BACKGROUND OF THE INVENTION
(1). Field of the Invention
The present invention relates to semiconductor devices, and more particularly to multi-finger MOSFET structures suitable for high frequency operation.
(2). Description of Prior Art
Multi-finger MOSFET structures are conventionally used in high frequency applications, rather than a single gate, because the reduced resistances of multi-finger MOSFETs gives rise to improved high frequency performance. In addition, for the short channel lengths and large gate widths of modem MOSFETs, a single gate would be extensive in one dimension, posing a layout problem. This problem is alleviated in a multi-finger late since the gate width is distributed among the fingers. When the finger length is a significant fraction of the gate width, there will be moderate number of fingers, and the device will be essentially two-dimensional. However, for conventional multi-finger gate structures longer fingers are more resistive. Thus, for conventional multi-finger structures the high frequency performance requirement, which favors short fingers, is opposed to the efficient layout requirement, which favors longer fingers.
A conventional multi-finger MOSFET, covering an active region,
10
, which is surrounded by field oxide, is shown in
FIG. 1
PRIOR ART. Source/drain regions,
12
, are parallel to and disposed on opposite sides of channel regions, which are separated by gate oxide layers from polysilicon gate fingers,
14
, directly above. The cross sections
20
and
22
depicted in
FIGS. 2 and 3
PRIOR ART further illustrate the structure. For the sake of clarity only a few source/drain regions and polysilicon gate finger regions are explicitly shown in the active region. However it should be understood that the active region is completely covered by these regions. In the active region, defined by the surrounding field oxide,
24
, the surface of the underlying semiconductor substrate,
28
, contains parallel source/drain regions,
12
and gate oxide regions,
26
. Contacts to the source/drain regions,
12
, are made by vias,
16
, through a dielectric layer,
30
. Contacts to the polysilicon fingers are made over the field oxide,
24
, outside of the active region by vias
18
. When contact is made to the gate fingers at the edge of the active region so that the edges of the gate fingers are essentially shorted together, and similarly for the source regions and the drain regions, there results a significant reduction in resistance. This is because the resistive length has been reduced by a factor equal to the inverse of the number of fingers. When contacts,
16
, which connect to the source/drain regions through vias,
16
, in a dielectric layer,
30
are added further decreases in resistance can result. By shorting the contacts to the source regions together and shorting the contacts to the drain regions together the resistive paths in these regions are reduced leading to a lower resistance.
In U.S. Pat. No. 5,789,791, Bergemont discloses multi-finger MOS transistor structures with reduced gate resistance. Shorting together the ends of each of the gates reduces the gate resistance and this is accomplished in a variety of ways. Multiple contacts are used to the source and drain regions. A method to completely short the gate area is disclosed in U.S. Pat. No. 5,828,102 to Bergemont, which does not include contacts to the source and drain regions within the active area. U.S. Pat. No. 6,023,086 to Reyes et al, teaches a multi-finger MOS transistor with a stabilizing gate electrode and U.S. Pat. No. 5,990,504 to Morifuji et al. teaches a multi-finger MOSFET with reduced noise. A memory cell array is disclosed in U.S. Pat. No. 5,719,806 to Yamane et al.
SUMMARY OF THE INVENTION
As a consequence, it is a major objective of the invention to provide multi-finger MOSFET structures with improved high frequency performance, but that do not require a short finger length. In one embodiment, referred to as the “on gate” configuration, the configuration is essentially that of
FIG. 1
PRIOR ART with multiple contacts added to each gate finder. These added gate contacts are situated between source and drain contacts in a manner so that source and drain contacts are not beside gate contacts. Additional gate contacts reduce the gate resistance and thus improve the high frequency performance. Furthermore, by adding contacts, high frequency performance can be maintained even as the finger length is increased. In a preferred embodiment, referred to as the “gate chain” configuration, a series of isolated active areas are perpendicular to each polysilicon gate finger. Contacts to the polysilicon gates are made external to and on both sides of the active areas. In each active area a channel region is disposed under the polysilicon gate, a source region is disposed to one side of the polysilicon gate and a drain region is disposed to the other side. Contacts are made to each source and drain region. In the embodiments, the gate contacts are connected together by low resistance lines, the source contacts are similarly connected, as are the drain contacts.
Measurements were performed of three indicators of high frequency performance, the noise figure, Nfmin, the effective resistance, Rn, and the maximum frequency, fmax; for transistors with the gate chain configuration, the on gate configuration and with the configuration of
FIG. 1
PRIOR ART, denoted the normal configuration. With respect to Nfmin, the gate chain configuration is best and the on gate configuration is superior to the normal configuration. With respect to Rn, the on gate configuration is best and the chain gate and normal configurations are similar. With respect to fmax, the gate chain configuration is the best and the on gate configuration is superior to the normal configuration. Significant improvements are seen to accrue from the gate chain and on gate embodiments of the invention.
A structure is disclosed for a multi-finger transistor with improved high frequency performance. An array of isolated active regions is formed in a semiconductor substrate. A source region and a drain region are formed in each of the active regions and are disposed on either side of a central channel region. A gate oxide layer is formed over each channel region. Conductive gate fingers that extend over the gate oxide layers and also beyond the active areas are formed so that each gate finger constitutes a continuous conductive line providing and connecting the gates of a plurality of active regions. A dielectric layer is formed over the active regions and over the surrounding isolation regions. A conductive via is formed through the dielectric layer to each source region and to each drain region. For each gate finger a conductive via is opened between the active regions and at both ends of the finger. A contact region is formed over each conductive via. Conductive lines are formed connecting together all the contact regions disposed over source regions, connecting together all the contact regions disposed over drain regions and connecting together all the contact regions disposed over gate fingers.


REFERENCES:
patent: 4462041 (1984-07-01), Glenn
patent: 5034792 (1991-07-01), Kimura et al.
patent: 5719429 (1998-02-01), Yoshida et al.
patent: 5719806 (1998-02-01), Yamane et al.
patent: 5789791 (1998-08-01), Bergemont
patent: 5828102 (1998-10-01), Bergemont
patent: 5831316 (1998-11-01), Yu et al.
patent: 5990504 (1999-11-01), Morifuji
patent: 6023086 (2000-02-01), Reyes et al.
patent: 6140687 (2000-10-01), Shimomura et al.
patent: 03142844 (1991-06-01), None
patent: 2000156494 (2000-06-01), None

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