Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-08
2004-05-11
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170
Reexamination Certificate
active
06735118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a circuit and a method for providing an override voltage to control gates through boosting of a selected word line for TWIN metal oxide nitride oxide MONOS semiconductor memory.
More particularly this invention relates to providing a means of using capacitive coupling between selected word lines and neighboring control gates to boost the voltage for the program, erase or read modes of MONOS memory.
2. Description of Related Art
High density flash memory arrays have been described in previous patents.
U.S. Pat. No. 6,011,725 (Eitan) “Two Bit Non-volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” describes a memory cell which uses charge trapping within various layers of the memory cell cross-section to store information. A single word gate has an underlying single oxide-nitride-oxide (ONO) composite layer in which electrons are trapped at two separate locations within the nitride layer. Thus, two hard bits of data can be stored under a single word gate, which roughly doubles the cell density.
The features of Twin MONOS memory cell structures distinctive of other flash and MONOS EEPROM cells, has been documented in U.S. Pat. No. 6,255,166 B1, “Nonvolatile memory cell, method of programming the same and nonvolatile memory array”, by S. Ogura, et. al, and U.S. patent application Ser. No. 09/810122, “Array architecture of nonvolatile memory and operation method”, by Y. Hayashi, et. al., submitted on Mar. 19, 2001.
FIG. 1
gives a cross-section of a Twin MONOS memory array. A single memory cell CELL[x] is composed of a control gate CG[x], a bit diffusion junction BL[x] and two halves of a word gate. In particular, the 2-bit nature of a cell is allowed through its structure composed of two separate nitride layers ML, MR residing in the oxide under two control gate components CG_L and CG_R, respectively. The side wall polysilicon control gates CG_L and CG_R may be physically or electrically connected to form the shared control gate CG[x] polysilicon. The bit diffusion BL[x] lies beneath the oxide under the control gate CG[x]. The 2-bit nature of a cell can be realized by selecting the left or right side of a selected cell through application of specific voltages to the control gates, bit line diffusions and word gates of the selected cell and the neighbor cells. The control gate lines are unique to the twin MONOS structure and provide an extra degree of control in choosing between the left or right side of the selected cell. However, the control gate lines also require additional decoding circuitry compared to other types of dual bit cells. Appropriate voltages need to be applied to the selected control gate CGs, as well as to an override neighbor CGo. In order to select one memory storage site, it is necessary to mask the threshold of the neighboring memory storage site by an override voltage. This voltage is usually higher than that of the voltage applied to the selected control gate CGs during read. For technologies with power supplies of 1.8V and below, the override voltage VCGo is usually higher than the power supply voltage, typically in a range of 2.5 to 3.0V. If for read or program operations, cell[X] is selected, then the corresponding control gate CGs is selected. When a memory site is targeted, then the word line adjacent to the side is also selected as WLs, and the control gate CGo on the other side of the word line is applied an override voltage VCGo.
An example of a Twin MONOS bit diffusion array is given with array version A in FIG.
1
and
FIG. 2
, based on U.S. Pat. No. 6,255,166 B1. This array consists of a plurality of memory cells, a plurality of word-lines
110
, control gate-lines
130
, and bit-lines
180
connected to the cells. One word line (WL) connects a row of N cells, the word line polysilicon connected throughout the entire word line, over and between the control gate polysilicon lines. In
FIGS. 1 and 2
, there are M control gate lines
130
,
220
equal to the number of bit-lines, both of which are parallel to each other and perpendicular to the word lines. During any read, program, or erase mode, one in every Y cells on one WL is selected. Therefore, CG drivers and CG decoders for selecting one in every Y control gate line are connected to the memory matrix, along with BL drivers and BL decoders for selecting one in every Y bit line. WL driver and WL decoders are also connected to the matrix, which provide the correct voltages to the memory word lines for selection of one WL. Referring to
FIG. 1
, when MR of Cell[X] is targeted, WL is selected, CG[x] is the selected CGs, and CG[x+1] is the override CGo.
Based on U.S. patent application Ser. No. 09/810122, another array version B is described in
FIGS. 3 and 4
. The relationship between the rows of word lines
310
,
430
and vertical bit line columns remains the same. However, in this metal bit array type, the control lines also run in parallel to the word lines, instead of the bit lines as in the diffusion bit array type Version A. Referring to
FIG. 3
, when MR of Cell[x] is targeted, then WL[x] is the selected word line WLs, CG[x] is the selected control gate line CGs and CG[x+1] is the override control gate line CGo. In Version A and B, one WL is selected during program and read. Also in both versions A and B, the decoders for the bit lines may be constructed so that one out of Y bit-lines are selected at the same time for 1 out of Y cells to be selected. In Version A however, for one out Y cells to be selected, the corresponding 1 out of Y control-lines need to be selected in a decoder scheme similar to the bit line's. The Version B control gate decoder is different than Version A in that only one control gate line
420
is selected with the one word line
430
, with additionally only one override neighbor control gate line.
The timing to setup the voltages on targeted WL, BL, and CG in a memory matrix is of particular importance to memory performance, especially during read. Load capacitance and resistance on the lines contribute to significant delays in switching between voltage states. The main control gate lines, and word gate lines are poly gates of cells connected together which have significant resistance and capacitance, depending on the length of the array. In
FIG. 4
, one main bit line
480
connects an entire column of cells through the diffusion, which also carries a significant capacitance and resistance. The resistance of the bit line is generally decreased by strapping/stitching the diffusion line at intervals to a metal bit line. However, in order to achieve high density and low cost, additional metal lines for both the word and control gate poly lines are not always feasible. Therefore, the voltage set up time is defined by the slowest line. The slowest delay is usually determined by the control gate line, which is very narrow and is difficult to silicide.
Conventionally, the voltage setup time for high performance read is reduced by decreasing the capacitance of the lines, thereby decreasing the charge up time. The capacitance for any of the lines can be cut with the addition of select transistors to the lines in question, creating sub-blocks within the memory matrix and decreasing the loads for the driver and decoders for the line. For example with matrix version A, to reduce the total bit line capacitance, a main bit line can be connected to sub bit lines via select gates. Thus the cell diffusion capacitance can be reduced to that of only one sub block in the memory matrix. The same concept of sub-blocking and select transistors may be similarly applied to the control gate lines and word gate lines. However, some penalties of the select gates are larger layout area, and additional concerns about sub block lines floating when unselected, and the select transistor size having suffi
Ogura Nori
Ogura Seki
Ackerman Stephen B.
Halo LSI, Inc.
Saile George O.
Tran M.
LandOfFree
CG-WL voltage boosting scheme for twin MONOS does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CG-WL voltage boosting scheme for twin MONOS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CG-WL voltage boosting scheme for twin MONOS will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3219803