CFET inverter having equal output signal rise and fall times by

Details CFET inverter having equal output signal rise and fall times by CFET inverter having equal output signal rise and fall times by

1986-03-17

1987-07-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307450, 307585, 307263, 357 42, H03K 17687

Patent

active

046820558

ABSTRACT:
A circuit comprises P-channel and N-channel field effect transistors. A conduction electrode, such as a drain, of one of the transistors is coupled to a conduction electrode of the other transistor. Means are provided for ensuring that the currents in the transistors when changing state, and hence the rise and fall times of an output signal of the transistors, are substantially equal. Preferably, the ensuring means comprises the channel length of the P-channel transistor being smaller than that of the N-channel device. Alternately, either the doping level or the width of the P-channel device can be greater than that of the N-channel device.

REFERENCES:
patent: 3651340 (1972-03-01), Cliff
patent: 4103188 (1978-07-01), Morton
patent: 4400636 (1983-08-01), Andrade
patent: 4405870 (1980-12-01), Eden
patent: 4418292 (1980-05-01), Cserhalmi
RCA COS/MOS Integrated Circuits Manual, RCA Solid State Division, Somerville, N.J., 1971, pp. 24-25.
Yang, Fundamentals of Semiconductor Devices, McGraw-Hill Book Co., New York, 1978, pp. 199-206.
"p-Channel (Al,Ga) As/GaAs Modulation-Doped Logic Gates", R. A. Kiehl et al., IEEE Electron Device Letters, vol. EDL-5, No. 10, Oct. 1984, pp. 420-422.

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