Centralizing the lock point of a synchronous circuit

Details Centralizing the lock point of a synchronous circuit Centralizing the lock point of a synchronous circuit

2006-07-11

2010-11-09

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S158000

Reexamination Certificate

active

07830194

ABSTRACT:
A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock (generated at the output of the delay line). A delayed version of the feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.

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