Centralized performance monitoring architecture

Details Centralized performance monitoring architecture Centralized performance monitoring architecture

1996-09-06

1999-03-09

Beausoliel, Jr., Robert W.

Excavating

39518501, 39518322, 371 51, G06F 1300

Patent

active

058812237

ABSTRACT:
A dynamically configurable arrangement for determining performance of a microprocessor. A plurality of functional units in a microprocessor are coupled to a performance counter, wherein the performance counter is incremented in response to occurrence of a predetermined event. A plurality of repeaters coupled between the plurality of functional units and the performance counter. Control circuitry coupled to the plurality of repeaters, wherein the control circuitry selectively enables the repeaters such that only one functional unit is coupled to the performance counter at a particular time.

REFERENCES:
patent: 4101964 (1978-07-01), Betts
patent: 4389538 (1983-06-01), White
patent: 4881191 (1989-11-01), Morton
patent: 4931972 (1990-06-01), Obata et al.
patent: 5537541 (1996-07-01), Wibecan
patent: 5557548 (1996-09-01), Grover et al.
patent: 5657253 (1997-08-01), Dreyer et al.
Brantley, W.C. et al, "RP3 Performance Monitoring Hardware," Parallel Computing Sys., ALM Press, NY, pp. 186-198, 1989.

Affiliated with

Also associated with

Rating

Centralized performance monitoring architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Centralized performance monitoring architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Centralized performance monitoring architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1330124