Centralized clock time error correction system

Details Centralized clock time error correction system Centralized clock time error correction system

1982-12-13

1984-12-25

Smith, Jerry

Excavating

364900, G06F 1100

Patent

active

044908210

ABSTRACT:
The present disclosure describes a system for substantially eliminating clock signal timing errors occurring between the signal paths of the various cabinets or modules of a large, high speed digital synchronous data processor. Such errors result from the most part because of the long cable lengths needed for coupling the cabinets to a master clock source. The present system provides a measure of the signal delay from the output of the master clock source through the elements of a given cabinet and permits corrective measures to be made at a single location within the cabinet without the necessity of accessing the large number of elements contained therein.

REFERENCES:
patent: 3325794 (1967-06-01), Jenkins
patent: 3456237 (1969-07-01), Collins
patent: 3530663 (1969-05-01), Marti
patent: 3927392 (1975-12-01), Caron
patent: 4115759 (1978-09-01), Besenfelder
patent: 4139147 (1979-02-01), Franke
patent: 4218771 (1980-08-01), Hogge
patent: 4330846 (1982-05-01), Colles
Mandra, R. R., "Skew Corrector", IBM Tech. Dis. Bulletin, _vol. 12, No. 4, Sep. 1969, p. 593.

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