Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1997-04-30
2001-02-06
Chauhan, Ulka J. (Department: 2776)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S522000, C712S243000
Reexamination Certificate
active
06184902
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to computer graphics systems and, in particular, to a centralized branch intelligence system and method for enabling efficient multiway logic branching in ROM-based control units of a high performance geometry accelerator.
BACKGROUND OF THE INVENTION
Computer graphics systems are commonly used for displaying graphical representations of objects on a two-dimensional display. Current computer graphics systems provide highly detailed visual representations of objects and are used in a variety of applications.
A typical computer that employs a computer graphics system is shown in FIG.
1
. Referring to
FIG. 1
, the computer
11
includes a central processing unit (CPU)
12
, a system memory
14
for storing software that is executed by the CPU
12
, a graphics system
16
for processing graphics data received from the CPU
12
, a local interface
18
configured to electrically interconnect the foregoing elements, and a display
21
connected to the graphics system
16
via a connection
22
and configured to display the image data generated by the graphics system
16
.
The graphics system
16
breaks down objects to be represented on the display
21
into graphics primitives. “Primitives” are basic components of a image data and may include points, lines, vectors, and polygons, such as triangles and quadrilaterals. Typically, hardware and/or software is implemented in the graphics system
16
in order to render, or draw, the graphics primitives that represent a view of one or more objects being represented on the display
21
.
Generally, the primitives of an object to be rendered are defined by the CPU
12
in terms of primitive data. For example, when a primitive is a triangle, the CPU
12
may define the primitive in terms of, among other things, x, y, and z coordinates and color values (e.g., red, green, blue) of its vertices. Additional primitive data may be used in specific applications. Rendering hardware in a rasterizer of the graphics system ultimately interpolates the primitive data to compute the final display screen pixel values that represent each primitive, and the R, G, and B color values for each pixel.
The graphics system
16
is shown in further detail in FIG.
2
. As shown in
FIG. 2
, the computer graphics system
16
includes one or more geometry accelerators
23
that are configured to receive vertex data from the CPU
12
and define the primitives that make up the view to be displayed. Each geometry accelerator
23
comprises a number of specialty control units
17
for processing the image data, including for example, a transform mechanism (TRANS)
24
for performing transformations on the vertex data, such as scaling or moving a vertex in space, a clip mechanism (CLIP)
26
for clipping portions of objects that extend beyond a boundary, a light mechanism (LIGHT)
28
for enhancing the image data by simulating light conditions, and a plane equation mechanism (PLANE)
32
for defining the primitives in terms of mathematical floating point plane equations. Each of the control units
17
is typically implemented via cell logic and as separate distinct state machines. The output of the geometry accelerator
23
, referred to as rendering data, is used to generate final screen coordinate and color data for each pixel and each primitive. The output
33
is passed to a floating point to fixed point (FP-TO-FIXED) transformation unit
34
, which converts the geometry accelerator output
33
to fixed point format
35
and which passes the value to a rasterizer
36
. The rasterizer
36
produces pixel data
37
, which is communicated to a frame buffer controller
38
and then to a frame buffer
42
. The frame buffer
42
serves to temporarily store the pixel data prior to communication to the display. The pixel data is passed from the frame buffer
42
through a digital-to-analog converter (DAC)
44
and then to the display
21
.
The operations of the geometry accelerator
23
are highly mathematical and computation intensive. One frame of a three-dimensionally dimensional (3D) graphics display may include on the order of hundreds of thousands of primitives. To achieve state-of-the-art performance, the geometry accelerator
23
may be required to perform several hundred million floating point calculations per second. Furthermore, the volume of data transfer between the CPU
12
and the graphics system
16
is very large. The data for a single quadrilateral may be on the order of sixty-four words of thirty-two bits each. Additional data transmitted from the CPU
12
to the geometry accelerator
23
includes light parameters, clipping parameters, and other parameters needed to generate the graphics image for the display
21
.
It is common in geometry accelerators
23
to have a stack of processing elements
52
, as illustrated in
FIG. 3
, including but not limited to, an arithmetic logic unit (ALU)
54
, a multiplier
55
, a divider
56
, a comparison mechanism
57
, a clamping mechanism
58
, etc., along with register and random access memory (RAM) work spaces
61
,
62
. The processor elements are typically shared by the plurality of specialty control units
17
. Each control unit
17
is capable of directing the processing activities of individual processor elements
52
to accomplish specific computational tasks.
To provide processor element access to each control unit
17
, adequate control line connectivity and access control should be established between the processor elements
52
and each control unit
17
. One solution to providing control line connectivity is illustrated in FIG.
3
and involves multiplexing the control lines between each control unit and each processor element
52
. A multiplexer (MUX)
66
of
FIG. 3
serves this purpose. The MUX
66
is controlled by a MUX control mechanism
68
. The MUX control mechanism
68
provides an enable signal
69
to the MUX
66
in order to control which one of the control units
17
is allowed to access the processor elements
62
at a given time. In operation, the MUX control
68
asserts an enable signal
69
pertaining to a particular control unit
17
to the MUX
66
and a go signal
72
to the particular control unit
17
. In turn, the particular selected control unit
17
generates operands and a processor start signal to begin a processing operation, which are ultimately forwarded to the stack
51
. The control unit
17
accesses the stack
51
and the specific desired processing element
52
via an appropriate connection
74
, MUX
66
, and connection
76
. The control unit
17
causes the operating processing element
52
to retrieve data from the input buffer
77
(usually, a FIFO buffer) and store a result(s) in an output buffer
82
(usually, FIFO buffer). The control unit
17
can initiate any number of operations via one or more of the processing elements
52
. When the control unit
17
is done with its turn, then it asserts a done signal
84
to the MUX control
68
. The MUX control
68
then asserts another go signal
72
to another control unit
17
, while providing an enable signal
69
corresponding to the next control unit
17
.
A problem with the foregoing design is the large number of gate levels that are required to implement the MUX
66
. Another problem is that the MUX
66
increases the time needed for signals to be communicated from the control unit
17
to the processing elements
52
. Gate delay alone is part of this increase. Loading also contributes to the time delay, even if a tri-state MUX
66
is employed to replace the multi-layered gate arrangement. Furthermore, the aforementioned problems are magnified as the number of control units
17
and the number of processing elements
52
are increased.
A heretofore unaddressed need exists in the industry for a system and method for better interfacing control units
17
with processing elements
52
in order to optimize the performance of a geometry accelerator in a computer graphics system.
SUMMARY OF THE INVENTION
The present invention provides for a centralized branc
Ashburn Jon L
Krech, Jr. Alan S.
McGrath Michael S
Rakel Ted
Rojas Edmundo
Chauhan Ulka J.
Hewlett--Packard Company
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