Central processor unit for executing instructions with a special

Details Central processor unit for executing instructions with a special Central processor unit for executing instructions with a special

1978-10-25

1980-12-23

Zache, Raulfe B.

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G06F 936

Patent

active

042413974

ABSTRACT:
A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

REFERENCES:
patent: 3293617 (1966-12-01), Cottet
patent: 3331056 (1967-07-01), Lethin et al.
patent: 3340513 (1967-09-01), Kinzie et al.
patent: 3400371 (1968-09-01), Amdahl et al.
patent: 3461433 (1969-08-01), Emerson
patent: 3614741 (1971-10-01), McFarland, Jr. et al.
Bell and Newell, Computer Structures: Readings and Examples, McGraw-Hill Book Co., New York (1971), pp. 588-601.
Honeywell Reference Manuel Series 400, Jan. 1970, pp. 205-227.

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