Central processor architecture implementing deterministic early

Details Central processor architecture implementing deterministic early Central processor architecture implementing deterministic early

1986-10-17

1990-10-30

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 928, G06F 702

Patent

active

049673513

ABSTRACT:
A central processor architecture implementating a deterministic, digit based, subterm computation and selective subterm combination early condition code analysis mechanism to provide for the early determination of the condition code that will be returned upon normal execution of a condition code setting instruction is described. The early condition code is returned sufficiently early to be combined with a branch mask to substantially reduce if not eliminate the need to interlock an immediately following conditional branch instruction. A wide variety of condition code setting instructions are handled by the deterministic condition code analysis mechanism of the present invention by implementing the mechanism to determine condition codes by the generation of digit subterms of the operand data accompanying condition code setting instruction and then combining the digit subterms in a predetermined manner selected based on the specific condition code setting instruction being executed. Branch decision analysis is performed by inclusion of the branch decision mask as a subterm selectively combined with the condition code subterms.

REFERENCES:
patent: 3825895 (1974-07-01), Larsen et al.
patent: 3881173 (1975-04-01), Larsen et al.
patent: 3961313 (1976-06-01), Bodner et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4373180 (1983-02-01), Linde
patent: 4578750 (1986-03-01), Amdahl et al.

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