Boots – shoes – and leggings
Patent
1987-09-25
1991-03-19
Williams, Jr., Archie E.
Boots, shoes, and leggings
364239, 364240, 3642443, 3642457, 364247, 3642545, 364259, 3642602, 3649278, 3649354, 364940, G06F 928, G06F 930, G06F 1200, G06F 1300
Patent
active
050016296
DESCRIPTION:
BRIEF SUMMARY
OPERATION FIELD OF THE INVENTION
The present invention relates to a central processing unit by which an effective operation is carried out without the need for a complex program. The present invention is applicable to a central processing unit of any type of computer, whether it is a general purpose, large scale computer or a microcomputer.
DESCRIPTION OF THE RELATED ART
A central processing unit (hereinafter referred to as a CPU) is provided with an arithmetic unit and a plurality of registers, and executes processes such as adding data transferred from a memory to a register and storing the result in a register. For such processes, the CPU is provided with an arithmetic and logic unit, a plurality of registers, a program counter for reading out each instruction from a main memory, a decoder for decoding the instructions, and so forth.
In the program stored in the main memory, instructions to command a data transfer between a certain register and the main memory or another register, and an operation on data between registers, etc. are included.
To improve the processing function of a CPU, the number of registers must be increased. However, when the number of registers is increased, the number of addresses specifying registers is also increased, and accordingly, the bit length of an instruction is increased, and this requires the use of a large storage area in the main memory.
To overcome this problem, a so-called stack system is provided in which a stored-type logical address is specified instead of increasing the number of registers. Data is added to the stack in the transferred sequence, and finally an operation is carried out with the transferred data and the previous data. However, a data transfer or an operation cannot be effected by the stack system unless the transferred sequence is memorized. Further, when data is read out from the stack by a pop operation, the data disappears from the stack. Therefore, when the data is to be kept in the stack after popping, a complex program becomes necessary. For example, the same data must be written by a new pushing or a new instruction must be made to double the amount of data to be pushed. Therefore, the conventional method utilizing the assembler language cannot be used, and support such as using a high-level language must be reinforced, and thus it is not entirely appropriate for effectively forming a small-scale program.
SUMMARY OF THE INVENTION
An object of the present invention is, in view of the above-mentioned problems in the conventional stack system, and based on the concept of carrying out a push operation on a pair of registers during writing and reading out not by pop operation but directly from each register during reading, to make it possible to increase the number of registers in a central processing unit without increasing the bit length.
Another object of the present invention is to provide a register construction in the above-mentioned central processing unit in which even a small-scale assembler language can be used for programming and thus the performance of the CPU be improved.
To attain the above objects, there is provided, according to the present invention, a central processing unit comprising an internal data bus, an arithmetic and logic unit, connected to the internal data bus, for executing an arithmetic operation and a logical operation; a plurality of registers, connected to the internal data bus, for storing the operated results and necessary data; and an instruction decoder, connected to the internal data bus, for decoding each instruction of the processing program read from a main memory. The plurality of registers and an additional register consist of a pair of registers.
A discriminating unit is provided for discriminating whether or not the decoded instruction output from the instruction decoder is a data transfer instruction from the internal data bus to one register of the pair of registers; and when it is discriminated as the data transfer instruction by the discriminating unit, the data from the internal data bus
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patent: 4323964 (1982-04-01), Gruner
patent: 4323981 (1982-04-01), Nakamura
patent: 4472773 (1984-09-01), Stanley
patent: 4521851 (1985-06-01), Trubisky et al.
patent: 4541045 (1985-09-01), Kromer, III
patent: 4771376 (1988-09-01), Kamiya
Igarashi Toshiyuki
Isobe Hideki
Kubo Yoshihiro
Murakami Joji
Yamada Kenji
Fujitsu Limited
Mohamed Ayni
Williams Jr. Archie E.
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