Central processing unit using dual basic processing units and co

Details Central processing unit using dual basic processing units and co Central processing unit using dual basic processing units and co

1993-06-17

1995-08-08

Beausoliel, Jr., Robert W.

Excavating

371 221, 39518209, 395448, 39518306, H04B 1700

Patent

active

054407249

ABSTRACT:
In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs. In a single precision test mode of operation, test signals internal to the BPUs are issued in complementary half-bytes on the normally redundant result busses and are directed to an external logic analyzer or other test equipment for conventional analysis. In addition, when no stores are being made but the BPUs are manipulating data, the test signals may be furnished to the external test equipment in the same manner, the type of operation, single or double precision, being irrelevant.

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