Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
1999-01-27
2002-12-24
Pan, Daniel H. (Department: 2171)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S023000, C712S227000
Reexamination Certificate
active
06499099
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is related to provide a central processing unit having a fixed length instruction for varying memory addresses, offsets and immediate data.
PRIOR ART
As it is apparent from
FIG. 5
, a conventional central processing unit comprises a register file
7
, including a GPR (General Purpose Register) configured to be suitable to an architecture that is a region to ease the access of a user and a SPR (Special Purpose Register) used for a special purpose; an instruction register
4
for latching an instruction patched from a memory; a decode/control portion
5
for decoding an OP code and an operand latched in the instruction register
4
and producing a predetermined control signal according to an instruction; a operating portion
6
for processing the instruction decoded in the decode/control portion
5
; a memory data register
1
for latching/buffering data when writing data in the memory or reading data from the memory; a memory address register
2
for latching/outputting an address counted in a program counter; and a control signal register
3
for buffering a control signal input from an outside source.
The instruction of the central processing unit called “Machine Language”, comprises an OP code which is expressed in an arrangement of binary bits and represents operation, and an operand which is subject to be operated by the OP code.
Seeing an ADD instruction as an example for OP codes and operands, ‘A=B+C’ is to add ‘B’ and ‘C’ to each other and store its result at ‘A’. Herein, ‘+’ is an OP code for representing the operation, and ‘A’, ‘B’ and ‘C’ are operands as objects to be operated upon. The above expression may be, ‘0001 0000 0001 0010’ if represented in a machine language, in which ‘0001’ is an OP code that symbolizes ‘+’ ‘0000’, ‘0001’ and ‘0010’ are operands that A, B and C are symbolized. The representation of the binary digit may be often embodied as a hexadecimal digit because reading is difficult. The representation of the hexadecimal digit in the above example becomes ‘0×1012’. In the machine language, the operand includes a register, a memory address, an offset and immediate data.
The number of the registers is limited to 32 in many cases. For example, if the number of registers is 16, it can be represented as an operand of 4 bits (2**4=16). But, in case of a memory address, a 32-bit central processing unit can use a memory of 4 G bytes. It needs a 32-bit address for its representation. Therefore, the operand length defining it becomes longer. In case of the offset and the immediate data, the operand length becomes longer similar to the case of the memory. If the operand length becomes longer, the length of the machine language gets longer. If the length of the machine language becomes longer, the program size is increased and the efficiency becomes bad.
Because of these reasons, each of the central processing units should have a technical method for representing the operand, efficiently. 80386 used in IBM-PC has a Multi-Byte Length Instruction. For example, the instruction machine language ‘MOVE’ of 80386 is defined based on the operand length as follows:
MOV AL,
12
→
B012
MOV AX,
1234
→
B8 34 12
MOV EAX,
12345678
→
66B8 78 56 34 12
Also, MC68000 has a Multi 16-bit Length Instruction similar to 80386. The variable Length Instruction, as described above, has an advantage of being able to represent any length of an operand, but has disadvantages in that it is difficult to process the instruction decoding and the exceptional situation, etc., because the length of the machine language is changed. The central processing unit having the variable length instruction is called CISC (Complex Instruction Set Computer).
On the other hand, in RISC (Reduced Instruction Set Computer) the length of the machine language is fixed. Given one example, MIPS-R3000, SPARC, ARM-7, etc. has a 32-bit fixed length instruction, SH-3 manufactured by Hitachi Co. has a 16-bit fixed length instruction. These fixed length instructions ease the instruction decoding, the exception process and the adoption of a pipe line to realize the high performance of the central processing unit because of the constant length of the machine language. On the contrary, it accompanies the restriction to the operand length because the instruction length is fixed.
For example, MIPS-R3000 has a memory of a 32-bit capacity. Nevertheless, an offset capable of representing in a machine language is a 16-bit and is a 32-bit central processing unit but the length of an immediate constant is limited to 16-bit. Thus, it becomes one of the reasons the program coding is difficult and its performance is deteriorating.
Also, an instruction, ‘MOVE’, is an operation for copying the content of one register to another register, in which the register operand has a 5-bit length because MIPS-R3000 has 32 registers. Assuming that the OP code for representing ‘MOVE’ is defined into a 6-bit, the fixed length instruction can be defined into 16-bit instruction. But, in order to use the fixed length instruction, 16-bit representable instruction is represented as a 32-bit one. But, the 32-bit fixed length instruction has disadvantages that the operand length is limited and has an unnecessary lengthy instruction.
Consider another example of TR-4101, TR-4101 has a 16-bit fixed length instruction and the function of extending a part of the fixed length instruction and the operand. For example, an instruction ‘LOAD’ forcing data to be fetched from a memory includes an OP code for representing ‘LOAD’ and a target register representing a register fetched and stored, an index register indicating the positions of an operand and a memory and an offset operand representing the offset from the operand and index. In order to represent these OP codes and various kind of operands on a 16-bit length instruction, TR-4101 limits the offset to a 5-bit. But, the 5-bit offset is not enough to represent the memory position. So, TR-4101 uses an instruction, ‘EXTEND’.
The instruction, ‘EXTEND’, includes an OP code of 5 bits and an immediate constant operand of 11 bits. Herein, the 11-bit immediate constant operand is interpreted according to the instruction positioned next to the instruction ‘EXTEND’. For example, when the ‘LOAD’ next to the instruction ‘EXTEND’ appears, the 11-bit immediate constant operand of the instruction ‘EXTEND’ and a 5-bit offset of the instruction ‘LOAD’ concatenated each other to represent the 16-bit offset.
The instruction extension technology of TR-4101 is only to extend the offset and the immediate constant into a 16-bit and does not resolve the limitation of the operand length that the conventional RISC central processing unit has. The operand extendable instruction makes the pointing-out of the operand different according to the existence of the instruction ‘EXTEND’. The instruction that the preceded instruction ‘EXTEND’ is concatenated is taken into one instruction. In other words, it has disadvantages that the exception process next to the instruction ‘EXTEND’ cannot be operated and the request in response to the peripheral apparatus cannot be processed in a real time.
Accordingly, in order to resolve these disadvantages and problems, an object of the invention is to provide a central processing unit having an extension instruction which takes advantages from a CISC and a RISC to represent all length of memory addresses and offsets and immediate data, to simplify an instruction decoder circuit using a fixed instruction as well as to facilitate the exception process, so that a pipe line and a MMU (Memory Management Unit) are simplified.
Another object of the present invention is to provide a central processing unit having an extension instruction to be able to return to the next routine which the process of extension instruction which the process of extension instruction is stopped after performing immediately an exception process procedure even though an exceptional situation next to the extension instruction happens.
SUMMARY OF
Asia Design Co., Ltd.
Chen Te
Pan Daniel H.
Suzue Kenta
Wilson Sonsini Goodrich & Rosati
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