Central processing unit for preventing program malfunction

Details Central processing unit for preventing program malfunction Central processing unit for preventing program malfunction

1996-12-30

1998-11-17

DeCady, Albert

39518502, 39580001, 395392, G06F 1100

Patent

active

058388966

ABSTRACT:
An improved CPU for preventing a program malfunction which is capable of preventing a malfunction of a program by resetting the CPU when an abnormal data is fetched from a memory due to a noise, which includes a program counter for designating an address of an instruction to be executed, a first instruction register for storing an instruction outputted from a memory by the program counter, a second instruction register for fetching an instruction stored in the first instruction register in accordance with a first internal clock signal, a third instruction register for fetching an instruction stored in the first instruction register in accordance with a second internal clock signal, a comparator, which is operated in accordance with an enable signal, for comparing whether instructions stored in the second instruction register and the third instruction register are identical, a reset controller for outputting a reset signal in accordance with an output signal from the comparator, an instruction decoder for decoding an operation code of an instruction stored in the third instruction register in accordance with an output signal from the comparator and for outputting a control signal and a program count value change instruction, and an execution unit for executing an instruction in accordance with a control signal from the instruction decoder.

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