Central processing unit for execution of orthogonal and non-orth

Details Central processing unit for execution of orthogonal and non-orth Central processing unit for execution of orthogonal and non-orth

1996-08-23

1998-06-30

Donaghue, Larry D.

395386, G06F 926

Patent

active

057747407

ABSTRACT:
In a central processing unit, the processes of two kinds of pipelines, i.e., a pipeline between instructions and pipelines in the instructions, can be executed in accordance with common pipeline control logic, wherein the control logic can be simplified and reduced.
Each part of a machine word determining at least one of each operand and operation is independently configured on a byte basis. The execution of each of instructions other than orthogonal instructions is pipeline-processed. The processes on at least one of each operand and operation in the orthogonal instructions are pipelined. The configurations of the pipelines in the orthogonal instructions and the pipeline between the instructions other than the orthogonal instructions are the same.

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Wainwirght et al, "Register Banks Boost 16/32-Bit CPU Performance"; 1987.
Maejima et al; "A 16-Bit Microprocessor with Multi-Register Bank Architecture"; 1988.
Kloker; "The Motorola DSP56000 Digital Signal Processor" IEEE Dec. 1986.

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