Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1993-09-28
2001-02-06
Banankhah, Majid (Department: 2755)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S520000
Reexamination Certificate
active
06184904
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a central unit for a process control system, for instance a storage-programmable control system which consists of a central unit and a number of peripheral devices which are connected to the central unit by a bus system, the central unit having at least one control processor system with a control processor for the processing of real-time tasks as well as at least one additional remainder processor system which is separate from the control processor system and has a remainder processor for processing tasks which are not time-critical.
Processor control systems are widely used. As a rule, they have two tasks to fulfill. Namely, on the one hand, an application program must be processed in real time and on the other hand, the outside world, for instance, other process control systems, must be communicated with, programs must be loaded and peripheral devices must be communicated with.
The implementation of both of these tasks by the same central unit has up to now had the result that the two tasks have negatively influenced each other. In particular, the so-called alarm-reaction time was relatively long and furthermore not accurately reproducible due to the carrying out of two tasks. Since a part of the computing capacity had to be used for communication and management tasks, the theoretically possible alarm reaction time could not be reached.
European Patent Document No. EP-A-0496,097 relates to a process control system which has a central unit similar to that described above. However, even in this system, the carrying out of the two above-mentioned tasks cannot take place separately. Upon access by the communication processor to the common bus system, the running of the application program must namely be interrupted by a control processor, since there is only one common bus.
SUMMARY OF THE INVENTION
The present invention to provides a process control system in which the two processor systems affect each other as little as possible. In particular, the full communication power of the central unit is capable of use and the alarm-reaction time is nevertheless low and reproducible.
The bus system has a control bus and a remainder bus, the control bus being connected to the control processor system and the remainder bus being connected to the remainder processor system. In this way, accesses of the processor systems to the peripheral units do not affect each other. The processor systems are therefore almost completely uncoupled from each other.
If the control processor system and the remainder processor system can be connected to each other via blockable coupling elements, for instance, tristate-HCMOS drivers, the processor systems can have access in each case to the other processor system.
This access is necessary, in particular, upon the starting up of the process control system in order that programs which are centrally stored can be copied into the corresponding processor system.
REFERENCES:
patent: 3676861 (1972-07-01), Ruth
patent: 3812468 (1974-05-01), Wollum et al.
patent: 4065809 (1977-12-01), Matsumoto
patent: 4144407 (1979-03-01), Zaffignani et al.
patent: 4200930 (1980-04-01), Rawlings et al.
patent: 4495569 (1985-01-01), Kagawa
patent: 4654654 (1987-03-01), Butler et al.
patent: 4713758 (1987-12-01), DeKelaita et al.
patent: 4907070 (1990-03-01), Wesolowski
patent: 5131092 (1992-07-01), Sackmann et al.
patent: 5210747 (1993-05-01), Gauthier et al.
patent: 5222213 (1993-06-01), Petty
patent: 5249299 (1993-09-01), Iwata
patent: 5281963 (1994-01-01), Ishikawa et al.
patent: 5317747 (1994-05-01), Mochida et al.
patent: 5325120 (1994-06-01), Kuehnle
patent: 5485579 (1996-01-01), Hitz et al.
patent: 5655106 (1997-08-01), Smith
patent: 0 088 805 (1983-09-01), None
patent: 0 298 396 (1989-01-01), None
patent: 0 496 097 (1992-09-01), None
patent: 2 250 106 (1992-05-01), None
IEEE Transactions On Vehicular Technology, vol. 39, No. 3, 1990, New York, Kamal N. Majeed: Dual-processor Controller with Vehicle Syspension Applications.
Burger Werner
Trummer Georg
Banankhah Majid
Kenyon & Kenyon
Siemens Aktiengesellschaft
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