Central processing unit architecture with symmetric instruction

Details Central processing unit architecture with symmetric instruction Central processing unit architecture with symmetric instruction

1994-03-07

1996-01-30

Geckil, Menmet

Boots, shoes, and leggings

395375, 364DIG1, 3642318, 364228, 364258, 3642954, G06F 1516, G06F 928, G06F 938

Patent

active

054887291

ABSTRACT:
An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.

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