Patent
1992-11-09
1995-11-21
Envall, Jr., Roy N.
395496, 395308, 395878, G06F 1300
Patent
active
054695449
ABSTRACT:
A microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invention, bits are used which may be programmed to disable and enable the address pipelining for the non-burst mode and burst mode transfers.
REFERENCES:
patent: 4851990 (1989-07-01), Johnson et al.
patent: 5029124 (1991-07-01), Leahy et al.
patent: 5058005 (1991-10-01), Culley
patent: 5146582 (1992-09-01), Begun
patent: 5289584 (1994-02-01), Thome et al.
Aatresh Deepak J.
Mathews Gregory S.
Nakanishi Tosaku
Envall Jr. Roy N.
Intel Corporation
Lintsai Paulina
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