Center phase verifying circuit and center phase verifying...

Details Center phase verifying circuit and center phase verifying... Center phase verifying circuit and center phase verifying...

2002-04-12

2003-07-22

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C375S371000, C375S375000

Reexamination Certificate

active

06597296

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to detection and correction of disturbance in the waveform of data signal. More particularly, it relates to a center phase decision circuit and to a center phase decision method in which an optimum center position is decided to process the data signal.
BACKGROUND OF THE INVENTION
There has so far been adopted a technique of serial to parallel converting data signal which is input as n-phase serial data, into a plural number of, for example, n parallel data.
FIG. 4
shows an example of a conventional circuit for a three-phase case. The circuit is comprised of a first flip/flop
81
, a second flip/flop
82
, and a ⅓ frequency divider
83
. This circuit receives data signal from a terminal IN_Data and clock for the data signal from a terminal IN_CLK.
As shown in an instance of
FIG. 5
, the ⅓ frequency divider circuit
83
generates and outputs, based on the input clock, three types of clocks with periods associated with the period of the original data signal, by a period thrice as long as the period of the original data signal. The three types of clocks are designated respectively by {circle around (1)}, {circle around (2)}, and {circle around (3)} in the timing waveforms of the frequency divider circuit in FIG.
5
.
In association with the three types of clocks, the second flip/flop
82
sequentially converts the data signal, input via the first flip/flop
81
at the clocked time point, into parallel data having a period thrice as long as the period of the original data signal.
SUMMARY OF THE DISCLOSURE
The conventional technique has, however, the following inconveniences:
As shown in an instance of the conventional circuit, shown in
FIG. 6
, if a jitter component (disturbance in the waveform) is produced in the data with respect to the clock, there is produced an area indefinite in phase, which gives rise to a high possibility of erroneous recognition or processing of the data signal.
In
FIG. 6
, illustrating timing waveforms in case of a conventional circuit as shown in
FIG. 4
, a disturbance is produced in the waveform of the input data signal and hence the period of the signal output from the flip/flop is not coincident with clock period, thus leading to incorrect readout of the data signal.
As shown in
FIG. 6
, there are some areas indefinite in phase in the output signal sequence of the first flip/flop
81
and the output of the second flip/flop
82
is caused to be indefinite in phase in case the frequency divided clock signal output from the frequency divider circuit is such a type as phase {circle around (1)} and {circle around (3)}.
Accordingly, it is an object of the present invention to overcome the above-described inconveniences of the prior art and to provide a phase correction circuit, a center phase decision circuit and a center phase decision method, in which, even when jitter component is produced in the data with respect to a clock signal, it is possible to accomplish correct processing of the data signal.
To achieve the foregoing and other objectives, a center phase decision circuit in accordance with one aspect of the present invention, which decides a center phase of data signal input as n-phase serial data, where n is an integer not less than 2, comprises: a serial to parallel converter circuit for outputting, via a plural number of output ports, parallel data obtained on serial to parallel conversion of said data signal at a period equal to n times the period of the data signal; a phase comparator circuit for comparing phases of parallel data output from each of said output ports for detecting phase non-coincidence; a counter for counting the number of times of detection of phase non-coincidence in each of said output ports by said phase comparator circuit; and a circuit for deciding said center phase based on the counted number of times of occurrences of phase non-coincidence.
In the center phase decision circuit in accordance with another aspect of the present invention, said serial to parallel converter circuit outputs parallel data, obtained on serial to parallel conversion of bits of respective periods of said data signal, at a period equal to n times the period of said data signal, from each of (n+1) output ports and said phase comparator circuit compares the phase of said parallel data output by the output port, to which the i-th period of said data signal, where i=1 to n, has been assigned, with the phase of the parallel data output by the output port to which the (i+1)-th period of said data signal has been assigned, to detect possible phase non-coincidence therebetween.
In the center phase decision circuit in accordance with further aspect of the present invention, there are provided a maximum value decision circuit for detecting the output port in which the number of times of occurrence of phase non-coincidence as counted by said counter is of a maximum value and a circuit for selecting the center phase based on a preset correspondence relationship between the combination of the output ports in which the number of times of occurrence of the phase non-coincidence is maximum and the output port in which the phase of the output parallel data is determined to be said center phase.
A phase correction circuit in accordance with another aspect of the present invention, which corrects phase disturbance of data signal input as n-phase serial data, where n is an integer not less than 2, comprises: a serial to parallel conversion circuit for outputting, via a plural number of output ports, parallel data obtained on serial to parallel conversion of said data signal at a period equal to n times the period of the data signal; a phase comparator circuit for comparing phases of parallel data output from each of said output ports for detecting phase non-coincidence; a counter for counting the number of times of detection of phase non-coincidence in each of said output ports by said phase comparator circuit; and a circuit for deciding said center phase based on the counted number of times of phase non-coincidence and for converting the serial to parallel converted data signal into serial data having the correct period based on the decided center phase to output resulting serial data.
In the phase correction circuit in accordance with another aspect of the present invention, said serial to parallel converter circuit outputs parallel data, obtained on serial to parallel conversion of bits of respective periods of said data signal, at a period equal to n times the period of said data signal, from each of (n+1) output ports and said phase comparator circuit compares the phase of said parallel data output by the output port, to which the i-th period of said data signal, where i=1 to n, has been assigned, with the phase of the parallel data output by the output port to which the (i+1)-th period of said data signal has been assigned, to detect possible phase non-coincidence therebetween.
In the phase correction circuit in accordance with further aspect of the present invention, there are provided a maximum value decision circuit for detecting the output port in which the number of times of occurrence of phase non-coincidence as counted by said counter is of a maximum value and a circuit for selecting the center phase based on a preset correspondence relationship between the combination of the output ports in which the number of times of occurrence of the phase non-coincidence is maximum and the output port in which the phase of the output parallel data is determined to be said center phase.
A method in accordance with another aspect of the present invention, which decides a center phase of data signal input as n-phase serial data, where n is an integer not less than 2, comprises the steps of:
serial to parallel converting said data signal to output parallel data obtained on the serial to parallel conversion at a period equal to n times the period of the data signal via a plural number of output ports;
comparing the phases of parallel data output from each of said output

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