Pulse or digital communications – Spread spectrum – Direct sequence
Patent
1988-01-28
1988-12-06
Griffin, Robert L.
Pulse or digital communications
Spread spectrum
Direct sequence
328155, H04L 708
Patent
active
047899964
ABSTRACT:
A center frequency high resolution digital phase-lock loop circuit (CF HRDPLL) is described with an input clock reference frequency which is equal to the output phase-locked frequency. The output is derived from delaying the input clock a variable number of gate delays ranging from no delay to one period of the input clock. A shift register controls the number of gate delays. A 360 degree phase detector initializes the shift register to provide no delay when the output is delayed by almost one period of the input clock and a phase retard correction occurs. An advance correction from a no delay condition causes a fast shift to occur to locate one period of delay while the output is held at no delay. The output is then switched to slightly less than one period of phase delay to allow further phase advance corrections to occur. Gate delay variations due to process, voltage and temperature are compensated for to provide a relatively constant clock phase correction.
REFERENCES:
patent: 4385396 (1983-05-01), Norton
patent: 4418318 (1983-11-01), Swagerty et al.
patent: 4574243 (1986-03-01), Levine
NEC Microcomputer Products 1987 Data Book, vol. 2 of 2, pp. 6-125, 6-26 and 6-127.
Griffin Robert L.
Huseman Marianne
Morris Jeffrey P.
Siemens Transmission Systems, Inc.
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