Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
1999-12-22
2002-07-02
Sircus, Brian (Department: 2839)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S071000
Reexamination Certificate
active
06413102
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to semiconductor chip fabrication. More particularly, the present invention relates to a center bond flip chip semiconductor carrier and a method for making and using it to produce a semiconductor device.
BACKGROUND OF THE INVENTION
Semiconductor device packaging techniques are well known. In some conventional packaged devices, a die is attached to a carrier, and contacts of each are electrically connected. In one such packaged device called a flip-chip device, a semiconductor chip is flipped and bonded with a carrier such that contacts of the die face and bond to contacts of the carrier.
With reference to
FIGS. 1-3
, a conventional center bond flip chip device
10
is shown as including a flipped die
30
and a carrier
11
. The carrier
11
has a flexible substrate
12
and an elastomeric cover material
14
. The elastomeric material
14
may be formed of a silicone or a silicone-modified epoxy. The elastomeric material
14
includes a first portion
15
and a second portion
17
of generally equal size. The flexible substrate
12
is formed of a material exhibiting high temperature stability as well as high mechanical rigidity. The substrate
12
may be a flexible tape, such as, for example, a polyimide tape. Two commercially available polyimide tapes, KAPTON® from E. I. DuPont Nemours and Company and UPILEX® from Ube Industries, Ltd., can be used to form the substrate
12
.
Conductive traces
16
a
,
166
b
,
16
c
are formed on the flexible substrate
12
and positioned below the elastomeric material
14
. The traces
16
a
,
16
b
,
16
c
may be deposited on the flexible substrate
12
in a variety of ways, the most preferred method being electrolytic deposition. Other suitable methods include sputter coating and laminating a sheet of conductive material and etching away excess material to form the traces.
A gap
20
separates the two portions
15
,
17
of the elastomeric material
14
. Conductive lands
18
a
,
18
b
,
18
c
are positioned on, respectively, the conductive traces
16
a
,
16
b
,
16
c
within the gap
20
. The die
30
has been removed from the
FIG. 1
for clarity of illustration of the lands
18
a
,
18
b
,
18
c
. As illustrated, the gap
20
is rectangularly shaped, although any configured gap will suffice as long as the conductive pads
18
a
,
18
b
,
18
c
are not covered by the elastomeric material
14
.
A die
30
is positioned on the elastomeric material
14
of the carrier
11
. The carrier
11
is electrically connected with the die
30
by way of suitable conductive connecting structures, such as, for example, inner lead solder balls or bumps
19
a
,
19
b
,
19
c
positioned on, respectively, the conductive pads or lands
18
a
,
18
b
,
18
c
. Conductive vias
22
a
,
22
b
,
22
c
respectively extend from each of the underside surfaces of the traces
16
a
,
16
b
,
16
c
. Outer lead solder balls or bumps
24
a
,
24
b
,
24
c
, or other conductive connecting structures, are located in electrical connection with each respective via
22
a
,
22
b
,
22
c
and serve to connect the traces
16
a
,
16
b
,
16
c
to a structure or common base for mounting components, such as, for example, a printed circuit board
35
. Preferably, the outer lead balls
24
a
,
24
b
,
24
c
are about 16 mils in diameter.
Conventional center bond flip chip semiconductor devices have several disadvantages, particularly as die
30
sizes decrease and the contacts thereof are positioned closer together. One disadvantage is that adjacent traces
16
a
,
16
b
,
16
c
of the carrier
11
and their associated conductive lands
18
a
,
18
b
,
18
c
must likewise be positioned closer together to such an extent that the inner lead balls
19
a
,
19
b
,
19
c
will occasionally contact one another, thereby shorting out the semiconductor device. Another disadvantage is that in positioning the inner lead balls
19
a
,
19
b
,
19
c
on the conductive lands
18
a
,
18
b
,
18
c
, wicking of the solder balls onto the conductive traces may sometimes occur during the solder process, providing less of a solder ball surface to make good electrical contact between the die
30
bond pad and a conductive land
18
of the carrier
11
.
There is, therefore, a need for a center bond flip chip semiconductor device design which alleviates to some extent these disadvantages.
SUMMARY OF THE INVENTION
The present invention provides a carrier for a semiconductor device which includes a substrate, at least one conductive trace located on the substrate, the trace including a recessed seat sized and configured to receive a conductive connecting structure, for example, a solder ball, and an elastomeric covering material, the material including a gap in which the conductive connecting structure may be located in the recessed seat to provide a reliable electrical connection of the trace with a flipped semiconductor die.
The present invention further provides a semiconductor device including a semiconductor die electrically connected to a carrier. The carrier includes at least one conductive trace located on a substrate. The trace includes a recessed seat sized and configured to receive a conductive connecting structure to allow electrical connection of the trace with the semiconductor die.
The present invention further provides an electronic system which includes a semiconductor die, a carrier and a structure for mounting the carrier. The carrier has a substrate, a plurality of conductive traces located on the substrate, and an elastomeric covering material. Each trace includes a recessed seat having a cut out portion sized and configured to receive a conductive connecting structure. The elastomeric material includes a gap corresponding to the location of the recessed seats to allow electrical connection of the traces with the semiconductor die.
The present invention further provides a method for making a carrier for a semiconductor die. The method includes locating at least one conductive trace on a substrate, and creating a recessed seated portion on the trace, which recessed seated portion can be used to seat a conductive connecting structure used for interconnecting the carrier to a semiconductor die.
The present invention further provides a method of making a semiconductor device. The method includes forming a carrier and electrically connecting the carrier with a semiconductor die. The forming includes locating at least one conductive trace on a substrate, creating a recessed seated portion on the trace, and affixing a conductive connecting structure which is coupled to the semiconductor die to the recessed seated portion.
The foregoing and other advantages and features of the invention will be more readily understood from the following detailed description of the invention, which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 5400220 (1995-03-01), Swamy
patent: 5736456 (1998-04-01), Akram
patent: 5818697 (1998-10-01), Armezzani et al.
patent: 5880590 (1999-03-01), Desai et al.
patent: 6056557 (2000-05-01), Crotzer et al.
patent: 6114763 (2000-09-01), Smith
patent: 6140707 (2000-10-01), Plepys et al.
Jiang Tongbi
Wood Alan G.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Sircus Brian
Webb Brian S.
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