Multiplex communications – Communication over free space – Combining or distributing information via code word channels...
Reexamination Certificate
1999-03-02
2003-07-08
Yao, Kwang Bin (Department: 2662)
Multiplex communications
Communication over free space
Combining or distributing information via code word channels...
C375S142000, C375S150000, C370S335000
Reexamination Certificate
active
06590888
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CDMA (Code Division Multiple Access) cellar system, in particular, a CDMA cellar system, an optimum path detecting method, an apparatus thereof, a mobile portable apparatus, and a base station apparatus that allow a path timing to be obtained corresponding to the maximum reception level of reception data.
2. Description of the Related Art
In a digital mobile telephone system and a portable telephone system (cellar system) that use the CDMA system, RAKE/diversity receiving technologies and transmission power controlling technologies have been widely used as a CDMA cellar system in multi-path fading environments because of high secrecy, interference resistance, high communication capacity, and high quality communication.
Amount them, a reception path timing searching technology is important. The searching accuracy of the reception path timing largely affects characteristics of the RAKE/diversity receiving process of the CDMA cellar system.
As a first related art reference, a spread spectrum receiving apparatus disclosed in Japanese Patent Laid-Open Publication No. 8-340316 will be described.
FIG. 1
is a block diagram showing principal portions of a spread spectrum receiving apparatus. In
FIG. 1
, a received spread spectrum signal is supplied to a frequency converting circuit
121
. The frequency converting circuit
121
converts the spread spectrum signal into a low frequency signal. The low frequency signal is supplied to a first multiplying unit
122
of a first inversely spreading circuit. The first multiplying unit
122
multiplies the low frequency signal by a spread code P
2
generated by a shift register
132
(that will be described later). An output signal of the first multiplying unit
122
is supplied to a phase comparing circuit
124
.
The phase comparing circuit
124
compares the phase of the output signal of the first multiplying unit
122
with the phase of an output signal of a VCO
130
that varies the frequency of a generated signal. An output signal of the phase comparing circuit
124
is supplied to a low pass filter LPF
126
. The low pass filter LPF
126
smooths the output signal of the phase comparing circuit
124
. An output signal of the low pass filter LPF
126
is supplied as a control signal to the VCO
130
. The first multiplying unit
122
, the phase comparing circuit
124
, the LPF
126
, the VCO
130
, a frequency dividing circuit
127
, a spread code generating circuit
123
, and the shift register
132
compose a phase synchronizing circuit (namely, a phase locked loop: PLL). The PLL operates so that the phase difference between two input signals of the phase comparing circuit
124
becomes zero.
The output signal of the VCO
130
is also supplied to the frequency dividing circuit
127
in addition to the phase comparing circuit
124
. The frequency dividing circuit
127
divides the frequency of the output signal of the VCO
130
. The spread code generating circuit
123
generates a spread code P
0
corresponding to an output signal of the frequency dividing circuit
127
. In addition, the shift register
132
generates a plurality of spread codes P
1
to P
4
with difference phases corresponding to the spread code P
0
. The shift register
132
is composed of for example four staged registers. The spread code P
0
received from the spread code generating circuit
123
is successively transferred from the first staged register to the fourth staged register corresponding to a clock signal that is the output signal of the VCO
130
. An output signal of the first staged register is the spread code P
4
. Output signals of the second to fourth staged registers are the spread codes P
3
, P
2
, and P
1
, respectively. The spread codes P
1
, P
2
, P
3
, and P
4
delay from the spread code P
0
by four clock pulses, three clock pulses, two clock pulses, and one clock pulse of the output signal of VCO
130
, respectively.
The spread code generating circuit
123
is composed of for example a shift register and an exclusive OR gate. The spread code generating circuit
123
is a well-known circuit that generates an M code sequence corresponding to the clock signal that is the output signal of the VCO
130
. The spread codes P
1
, P
2
, P
3
, and P
4
synchronize with the output signal of the VCO
130
. The spread codes P
1
, P
2
, P
3
, and P
4
are supplied to second inversely spreading circuits
133
,
134
,
135
, and
136
, respectively. The second inversely spreading circuits
133
to
136
inversely spread the spread spectrum codes.
Output signals of the second inversely spreading circuits
133
to
136
are supplied to a level detecting circuit
137
. The level detecting circuit
137
detects levels of the output signals of the second inversely spreading circuits
133
to
136
by envelop detecting method and extracts correlations between the spread spectrum signals and spread codes. Output signals of the level detecting circuit
137
are supplied to a determining circuit
138
. The determining circuit
138
determines a signal with the highest level of the output signals of the second inversely spreading circuits
133
to
136
. An output signal of the determining circuit
138
is supplied to a switching circuit
139
. The switching circuit
139
selects a signal with the highest level from the output signals of the second inversely spreading circuits
133
to
136
corresponding to the determined result of the determining circuit
138
.
An output signal of the switching circuit
139
is supplied to a BPF
128
. The BPF
128
limits the frequency band of the output signal of the switching circuit
139
. An output signal of the BPF
128
is supplied to a demodulating circuit
129
. The demodulating circuit
129
demodulates the output signal of the BPF
128
. The plurality of second inversely spreading circuits detect a level with the highest correlation. Thus, the synchronization of spread spectrum codes can be securely acquired and tracked.
Next, a second related art reference disclosed in Japanese Patent Laid-Open Publication No. 7-193525 will be described. The second related art reference relates to a synchronizing method for a radio communication network, in particular, to a synchronizing method for a radio communication network of which each repeating station repeats a synchronous signal at a transmission timing fixedly assigned with an ultra-frame using frequency hopping type spread spectrum modulation (FH-CDMA) and a time division multiple access (TDMA). In the second related art reference, the reception levels of synchronous signals received from individual repeating stations are successively compared for individual ultra-frames. The transmission timing with the maximum reception level is stored. In the next ultra-frame, an operation corresponding to the synchronous signal at the transmission timing stored in the preceding ultra-frame is repeated for individual ultra-frames. Thus, an adjacent station with the highest reception level can be tracked. Consequently, a signal can be synchronously and stably received.
Next, a third related art reference disclosed in Japanese Patent Laid-Open Publication No. 9-261128 will be described. The third related art reference relates to a synchronizing apparatus disposed in a spread spectrum communication receiver for use with a digital mobile radio communication system. The synchronizing apparatus comprises a DLL for synchronously tracking a PN (Pseudo-Noise) signal against sampling data received from an A/D converter that converts a reception signal into a digital signal, a searching unit for searching a path from which a reception signal with the maximum power is obtained, and a data demodulating correlator for inversely spreading and demodulating the reception signal.
The searching unit has a searching PN generator for generating a PN phase of the PN signal, a searching correlator for correlating sampling data with the PN signal and outputting correlation value data, a data buffer for storing the correlation v
Hoang Thai D
NEC Corporation
Sughrue & Mion, PLLC
Yao Kwang Bin
LandOfFree
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