Multiplex communications – Communication techniques for information carried in plural... – Adaptive
Reexamination Certificate
1998-01-28
2001-06-26
Nguyen, Chau (Department: 2663)
Multiplex communications
Communication techniques for information carried in plural...
Adaptive
C370S474000
Reexamination Certificate
active
06252887
ABSTRACT:
The present invention relates to a method of cell to frame conversion management for packet-switched data communications, and more particularly to a method of managing the conversion between Asynchronous Transfer Mode (ATM) cells and Frame Relay frames without the need for providing intermediate buffering of the converted data packets.
Frame Relay is a connection-oriented, variable bit-rate protocol which is widely used to provide Local Area Network (LAN) and LAN-Interconnect Services. Frame Relay uses a unit of data called a frame, which may be of variable length depending upon the amount of data to be transmitted, and the characteristics of the network to be used. However, a fundamental characteristic of frame relay which is of the utmost importance in the context of the present invention is that consecutive frames transmitted on the same network may be of markedly different sizes.
Asynchronous Transfer Mode (ATM) which may also be referred to as Cell Relay, is a connection-less variable bit-rate architecture which corresponds approximately to layers 1 and 2 of the Open Systems Interconnection (OSI) reference model for data communications. ATM uses a unit of data called a cell, which is of a fixed size of 53 octets. The individual functions of each octet within an ATM cell as to whether they carry network control and addressing information, error checking information or the actual data payload are determined by the ATM Adaptation Layer (AAL) protocols which correspond approximately to layers 2 and 3 of the OSI reference model. There are currently several different AALs which each provide different functions and services, however in the context of the present invention it is merely important that it is understood that all ATM cells must be of a fixed size, no matter which adaptation layer is to be used.
ATM has recently emerged as the architecture of choice for the next-generation broadband networks, as it has proved to be extremely versatile in handling different volumes and types of network traffic, including packetised voice and video traffic as well as the more traditional data communications. Although predominantly providing connection-less protocols, a connection-oriented service may be provided though the use of the Service Specific Connection Oriented Protocol (SSCOP) The provision of Virtual Channels (VC) and Virtual Paths (VP), used in conjunction with advanced traffic policing and shaping algorithms enabling ATM to appear as if it is able to reserve bandwidth on a network and thus guarantee high-speed, low-error rate data communications.
There is a requirement for the emerging ATM broadband networks to interwork with existing narrow-band LAN services, and an interworking function is therefore required between the LAN and the ATM network. WO 93/26107 relates to an “ATM-ETHERNET portal/concentrator” which allows for transparent connection of an ETHERNET type LAN into an ATM network. By using a double port memory the construction becomes simple, the processor power slight, and the capacity high as there is no need to copy data cells.
WO 95/00829 discloses a device for providing a bridge from a LAN into an ATM network, which uses the AAL5 protocol. The bridges make use of a connection-less data services function by means of Broadband Data Service Servers (BDS) to provide transmission to and from the LAN without buffering. The device is particularly adapted for providing IP over an ETHERNET LAN, and preferably the respective local network will be connected via only one BDS, while the transmission in the BDS network is in streaming mode.
The present invention is aimed at providing an interworking function to interface a frame relay LAN to an ATM network. According to the present invention a method of transferring data from a broadband packet-switched data communications network which uses data packets of a fixed size to a narrow-band packet-switched data communications network which uses data packets of variable size, comprising the steps of:
queuing input fixed length data packets;
processing the data payloads of said input data packets received from said queue to line-encode said data so it may be transmitted in data packets of variable size;
generating output fixed-length data packets of the same size as the input fixed-length data packets for transmitting said processed data payloads to a fixed-length to variable length data packets conversion device;
wherein the generating step comprises holding any input data packet in said input queue until all its data payload has been processed and passed into a said output data packet and reprocessing the input data packet in the event that not all of its data payload has been so passed whereby the remainder of the data payload of said held packet is passed to the next output data packet.
An advantage of the present invention is that it removes the need for a separate buffer to store the output of the cell to frame conversion by making use of a cell queueing function. This saves critical board space by removing not just the memory itself, but also the associated controller logic and context memory for that logic. Board area savings are critical within the field of high density interface applications, reducing the cost of, minimising the manufacturing steps required for, and improving the reliability of each board.
A further advantage of the present invention is that due to the lack of cell buffering, generic processing hardware blocks consisting of an FPGA, Processor, and context memory can be used to provide conversion in each direction ie. from the cell to frame and vice versa. There are many data communications applications which could make use of such a module and re-use saves both design effort and manufacturing costs. The next generation FPGAs may incorporate gate array structures integrated with the processor and memory on a single IC, thus making the generic processing block of the present invention more attractive.
REFERENCES:
patent: 5420858 (1995-05-01), Marshall et al.
patent: 5459723 (1995-10-01), Thor
patent: 5490140 (1996-02-01), Abensour et al.
patent: 5528590 (1996-06-01), Iidaka et al.
patent: 5809012 (1998-09-01), Takase et al.
patent: 5848354 (1998-12-01), Kamalski
patent: 593843 (1994-04-01), None
patent: 9326107 (1993-06-01), None
patent: 9724842 (1996-12-01), None
Boakye Alexander O.
Malin Haley & DiMaggio, P.A.
Nguyen Chau
Northern Telecom Limited
LandOfFree
Cell to frame conversion management does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cell to frame conversion management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cell to frame conversion management will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2452102