Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Patent
1995-08-21
1997-04-08
Olms, Douglas W.
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
370395, 370427, H04Q 1104
Patent
active
056194951
ABSTRACT:
This invention provides a cell switching apparatus having buffer memories in which accesses of a plurality off cells can be implemented in one-cell time. The cell switching apparatus arranges a plurality of buffer memories, in which accesses of a plurality of cells can be performed, in parallel, and schedules a score table so that the writing and reading out operations may not overlap. Accordingly, the incoming lines may be increased lip to (the number of incoming lines n)=(the number of buffer memories p-1).times.(the number of outgoing lines m) without increasing the access speed of the buffer memories.
REFERENCES:
Jean-Pierre Coudreuse & Michel Servel "Prelude:An Asynchronous Time-Division Switched Network" 1987 IEEE pp. 0769-0773.
Y. Sakurai, et al. "Large Scale ATM Multi-Stage Switching Network with Shared Buffer Memory Switches" International Switching Symposium 1990 pp. 121-126.
K. Oshima, et al. "A New ATM Switch Architecture Bsed on STS-Type Shared Buffering and Its LSI Implementation" IEICE 1992 Oct., pp. 359-363.
William Stallings, "Data and Computer Communications", 2nd ed., Macmillan Pub. Co., pp. 215-218, 1985.
Oshima Kazuyoshi
Saito Hirotaka
Sasaki Yasuhito
Tsuzuki Munenori
Yamada Hirotoshi
Mitsubishi Denki & Kabushiki Kaisha
Olms Douglas W.
Phillips Matthew C.
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