Cell-structured digital multiplier of semi-systolic construction

Details Cell-structured digital multiplier of semi-systolic construction Cell-structured digital multiplier of semi-systolic construction

1985-08-05

1988-05-31

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

047485833

ABSTRACT:
A digital multiplier which has cells arranged in a plurality of rows and columns wherein the rows are assigned to different groups of partial product bits. Sum paths and carry paths are provided which connect the individual cells to each other and at their ends emit signals from which the product bits are formed. The multiplicand bits are stored intermediately together with the sum and carry signals formed in a row and are simultaneously forwarded to the next row in accordance with a pipelining process. It is desired to obtained the least possible delay in feeding a multiplier bit into all the cells of a row so as to achieve short range transit time of the signals between the output of two consecutive rows and this is achieved with a logic link element which is used to form a partial product bit which is contained in a cell which proceeds the row and in which this partial product bit is added to sum signals and carry signals. One of the cells of the following row contains a full adder which is connected to the output of the logic link with a connection line which is provided with a shift register stage. The invention can be used for integrated circuit for digital data processing.

REFERENCES:
patent: 3691359 (1972-07-01), Dell et al.
patent: 3900724 (1975-08-01), Melver et al.
patent: 4369500 (1983-01-01), Fette
patent: 4432066 (1984-02-01), Benschop
patent: 4441158 (1984-04-01), Kanuma
Effective Pipelining of Digital Systems-Jump and Ahuja Transactions on Computers, vol. C-27, No. 9, Sep. 1978.

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