Boots – shoes – and leggings
Patent
1989-05-02
1993-04-13
Lee, Thomas C.
Boots, shoes, and leggings
3642328, 3642678, 3642683, 3642692, 3649494, 36494991, 3649426, 3649255, 3649278, 364DIG1, 395325, G06F 1314
Patent
active
052030059
ABSTRACT:
A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known delay from function logic to function logic of the cells.
REFERENCES:
patent: 3913072 (1975-10-01), Catt
patent: 4038648 (1977-07-01), Chesley
patent: 4471483 (1984-09-01), Chamberlain
patent: 4489397 (1984-12-01), Lee
patent: 4493055 (1985-01-01), Osman
patent: 4517659 (1985-05-01), Chamberlain
patent: 4519035 (1985-05-01), Chamberlain
patent: 4910665 (1990-03-01), Mattheyes et al.
patent: 4928022 (1990-05-01), Marum
patent: 4943946 (1990-07-01), Brent
patent: 5031139 (1991-07-01), Sinclair
patent: 5058001 (1991-10-01), Li
patent: 5068823 (1991-11-01), Robinson
patent: 5072424 (1991-12-01), Brent et al.
patent: 5084838 (1992-01-01), Kajimoto et al.
"Chip Frame" Scheme for Reconfigurable Mesh-Connected Arrays, P. D. Franzon & S. K. Tewksbury, Proc. IFIP Int'l Workshop on WSI, 1987, 10 pages (unnumbered).
A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield, Will Moore, Proceedings of the IEEE, vol. 74, May 1986, pp. 684-698.
A WSI Approach Towards Defect/Fault-Tolerant Reconfigurable Serial Systems, Wei Chin, John Mavor, Peter B. Denyer, and David Renshaw, IEEE Journal of Solid State Circuits, vol. 23, No. 3, Jun., 1988, pp. 639-646.
WSI-The Challenge of the Future, Proceedings IEEE Conference on VLSI and Computers, May, 1987, pp. 531-542.
Systolic System Processing Systems, edited by Earl E. Swartzlander, Jr., (Marcel Dekker, Inc., New York), 1987, pp. 299-326.
Architectures, M. J. Schute and P. E. Osman (Adam Hilger, 1986), Chapter 4.4, pp. 169-178, "Cobweb-A Reduction Architecture".
Wafer Scale Integration, G. Saucier and J. Trilhe (Editors), Elsevir Science Publishers, 1986, pp. 255-270, "Switch Design for Soft Configurable SWI Systems" by Manolis G. H. Katevenis et al.
Asynchronous and Clocked Control Structures for VLSI-Based Interconnection Networks, Mark A. Franklin and Donald F. Wann, Proceedings, 9th Symposium on Computer Architecture, Apr., 1982, pp. 50-59.
An Approach to Highly Integrated, Computer-Maintained Cellular Arrays, Frank B. Manning, IEEE Transactions on Computers, vol. C-26, Jun., 1977, pp. 536-552.
Wafer Scale Integration and Two-Level Pipelined Implementations of Systolic Arrays, H. T. Kung and Monica S. Lam, "Journal of Parallel and Distributed Computing," 1984, pp. 32-63.
Brighter Prospects for Wafer Scale Integration, Roger Dettmer, "Electronics and Power," Apr., 1986, pp. 283-288.
200Mb Wafer Memory, Neal MacDonald, Gordon Neisch, Allan Sinclair, et al., 1989 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 240-241 (Feb. 1989).
Kim Ken S.
Lee Thomas C.
LandOfFree
Cell structure for linear array wafer scale integration architec does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cell structure for linear array wafer scale integration architec, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cell structure for linear array wafer scale integration architec will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1161634