Cell sequence number synchronization system and method

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

Reexamination Certificate

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C370S516000

Reexamination Certificate

active

10231217

ABSTRACT:
The present invention provides a system and method for enabling the synchronization of a switch and an interface device. Based on a comparison of cell sequence numbers included in cells received from the interface device to a current cell time within the switch, cell time adjustment information can be transmitted to the interface device. The cell time adjustment information is used by the interface device to determine the cell sequence number that is included in cells transmitted to the switch.

REFERENCES:
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patent: 5959980 (1999-09-01), Scott
patent: 5974103 (1999-10-01), Williams
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A 622-Mb/s bit/frame synchronizer for high-speed backplane datacommunication; Yoshimura, T. Kondoh, H. Matsuda, Y. Sumi, T.; This paper appears in: Solid-State Circuits, IEEE Journal of Publication Date: Jul. 1996 vol. 31, Issue: 7 On pp. 1063-1066.
OC-12c digital crossconnect switch; Basch, B. Moolenbeek, R. Samalam, V.K. Procanik, M.J.; This paper appears in: Selected Areas in Communications, IEEE Journal on Publication Date: Feb. 1996 vol. 14, Issue: 2□□On pp. 346-352□□.
Fast Switched Backplane for a Gigabit Switched Router; Nick McKeown; Department of Electrical Engineering□□Stanford University, Stanford, CA 94305-9030, 1999.
Scheduling in input-queued cell-based packet switches, Marsan, M.A. Bianco, A. Giaccone, P. Leonardi, E. Neri, F.; This paper appears in: Global Telecommunications Conference, 1999. GLOBECOM '99; Publication Date: 1999 vol. 2, On pp. 1227-1235 vol. 2 Meeting Date: Dec. 5, 1999-Dec. 9, 1999.
“Conservative Synchronization Algorithms—Chapter 3”—pp. 51-91, 1999.

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