Multiplex communications – Pathfinding or routing – Store and forward
Reexamination Certificate
1998-08-25
2002-07-16
Patel, Ajit (Department: 2662)
Multiplex communications
Pathfinding or routing
Store and forward
C711S171000
Reexamination Certificate
active
06421351
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cell phase control device enabling a cell having no phase difference between writing and reading to be sent and received between circuits operative in response to a clock signal and a cell phase pulse independent of each other in digital asynchronous transfer mode (ATM) communication.
2. Description of the Related Art
Cell phase control devices of this kind are conventionally used for sending and receiving cells at a fixed length between circuits operative in response to a clock signal and a cell phase pulse independent of each other.
One of conventional cell phase control devices, for example, is disclosed in Japanese Patent Laying-Open (Kokai) No. Heisei 4-220829, entitled “Cell Phase control Circuit”. The literature proposes a cell phase control circuit which, even when a write pulse or a read pulse is applied in a cycle not normal, automatically recovers after the restoration of input conditions to enable effects of a failure to be minimized.
FIG. 4
is a block diagram showing structure of such a cell phase control device as mentioned above. The cell phase control device shown in
FIG. 4
employs the same fixed size (fixed length) as the sizes of cell data to be written and cell data to be read.
FIG. 5
is a timing chart for use in explaining operation of writing to a memory and reading from the memory at the cell phase control device shown in FIG.
4
.
With reference to
FIGS. 4 and 5
, the size of a write region within a two-port RAM (Random Access Memory)
100
is fixed. Upon receiving input of a cell whose size is larger than the fixed write size as a basis, a write control unit
103
accordingly generates an internal write signal
113
equivalent to a fixed-length part of the cell corresponding to the write size of the two-port RAM
100
. As a result, only the data equivalent to the fixed length is written into the two-port RAM
100
, while surplus data is not written but abandoned. Cell data C
3
shown in
FIG. 5
, for example, is data whose length is longer than the fixed length by TX. The TX part of the cell data C
3
will not be written into the two-port RAM
100
but abandoned as surplus data.
In the conventional cell phase control device, a read control unit
104
also generates, with the fixed write size of the two-port RAM
100
as a basis, an internal read signal
123
of the fixed length in question to send cell data of the fixed length constantly.
As described in the foregoing, the conventional cell phase control devices are premised on that cell lengths of write and read pulses to be applied are of a fixed size. As to such data whose size is larger than the fixed size as data for controlling a device, surplus data other than data equivalent to the fixed length will be abandoned as described in the foregoing.
To avoid such a situation, data for controlling a device should be conventionally divided into a plurality of cells of a fixed length and then transferred or should be transferred through other path, making procedures complicated.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a cell phase control device which solves the above-described conventional problem and on the premise that a cell length of a write pulse signal or a read pulse to be applied is a fixed length, enables even data for controlling a device whose size exceeds the fixed length to change a phase using a transmission path for use in transfer of data of the fixed length without abandoning the data.
According to one aspect of the invention, a cell phase control device which sends and receives cells between circuits operative in response to a clock signal and a cell phase pulse independent of each other in digital asynchronous transfer mode communication, comprises
a plurality of buffers,
writing means responsive to a write pulse signal and a write clock signal for writing cell data into the plurality of buffers in order, and writing cell data simultaneously into the plurality of buffers as required,
reading means responsive to a read pulse signal and a read clock signal for reading the cell data from the plurality of buffers in order, and
control means for arbitrating writing operation by the writing means and reading operation by the reading means, wherein
the writing means, after writing one cell data into one of the plurality of buffers, writes the subsequent one cell data into other one of the plurality of buffers, as well as continuously writing, for a fixed time period, the subsequent cell data into the buffer into which the one cell data has been written.
In the preferred construction, the buffer is a two-port RAM.
In another preferred construction, cell data to be read or written from/into the buffer are of two sizes, and the writing means starts writing, into one of the plurality of buffers, at the top of one cell data to write, irrespective of the size of the one cell data, data in the amount equivalent to cell data of a larger size.
In another preferred construction, cell data to be read or written from/into the buffer are of two sizes, and the reading means reads cell data written in the buffer on a cell basis.
In another preferred construction, cell data to be read or written from/into the buffer are of two sizes, and
the reading means
when cell data of a larger size is written in the buffer, reads all the data written in the buffer, and
when cell data of a smaller size and part of the other cell data are written in the buffer, reads only the cell data of the smaller size.
In another preferred construction, cell data to be read or written from/into the buffer are of two sizes,
the writing means starts writing, into one of the plurality of buffers, at the top of one cell data to write, irrespective of the size of the one cell data, data in the amount equivalent to cell data of a larger size, and
the reading means reads cell data written in the buffer on a cell basis.
In another preferred construction, cell data to be read or written from/into the buffer are of two sizes,
the writing means starts writing, into one of the plurality of buffers, at the top of one cell data to write, irrespective of the size of the one cell data, data in the amount equivalent to cell data of a larger size, and
the reading means
when cell data of the larger size is written in the buffer, reads all the data written in the buffer, and
when cell data of a smaller size and part of the other cell data are written in the buffer, reads only the cell data of the smaller size.
Also, the cell phase control device further comprises selective output means for receiving cell data read from the plurality of buffers and selectively switching to output one of the cell data.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.
REFERENCES:
patent: 5311517 (1994-05-01), Senoo
patent: 5319596 (1994-06-01), Kogure
patent: 5436863 (1995-07-01), Kogure
patent: 5765186 (1998-06-01), Searby
patent: 62-64192 (1987-03-01), None
patent: 1-215137 (1989-08-01), None
patent: 2114732 (1990-04-01), None
patent: 4-220829 (1992-08-01), None
patent: 7-58753 (1995-03-01), None
patent: 7-297918 (1995-11-01), None
patent: 7-307797 (1995-11-01), None
patent: 9205434 (1997-08-01), None
patent: 9-224080 (1997-08-01), None
Office Action Issued by the Japanese Patent Office for the Corresponding Japanese Application Dated Feb. 9, 1999 and an English Translation thereof.
Japanese Office Action issued Nov. 2, 1999 in a related application with English translation of relevant portions.
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Patel Ajit
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