Cell modeling in the design of an integrated circuit

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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Details

C703S014000, C703S015000, C703S019000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06985843

ABSTRACT:
The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.

REFERENCES:
patent: 5802349 (1998-09-01), Rigg et al.
patent: 5818726 (1998-10-01), Lee
patent: 5831863 (1998-11-01), Scepanovic et al.
patent: 5914887 (1999-06-01), Scepanovic et al.
patent: 5930499 (1999-07-01), Chen et al.
patent: 5984510 (1999-11-01), Guruswamy et al.
patent: 6006024 (1999-12-01), Guruswamy et al.
patent: 6058252 (2000-05-01), Noll et al.
patent: 6256768 (2001-07-01), Igusa
patent: 6269467 (2001-07-01), Chang et al.
patent: 6292929 (2001-09-01), Scepanovic et al.
patent: 6298468 (2001-10-01), Zhen
patent: 6308309 (2001-10-01), Gan et al.
patent: 6367056 (2002-04-01), Lee
patent: 6415426 (2002-07-01), Chang et al.
patent: 6446239 (2002-09-01), Markosian et al.
patent: 6449761 (2002-09-01), Greidinger et al.
patent: 6457159 (2002-09-01), Yalcin et al.
patent: 6519749 (2003-02-01), Chao et al.
patent: 6536028 (2003-03-01), Katsioulas et al.
patent: 6539531 (2003-03-01), Miller et al.
patent: 6557153 (2003-04-01), Dahl et al.
patent: 6625787 (2003-09-01), Baxter et al.
patent: 6629630 (2003-10-01), Adams
patent: 6756242 (2004-06-01), Regan
patent: 6757874 (2004-06-01), Dahl et al.
Lefebvre et al., The Future of Custom Cell Generation in Physical Synthesis, ACM 1997.
Senouci et al., Timing Driven Floorplanning on Programmable Hierarchical Targets, ACM 1998.
Dutt et al., Efficient Incremental Rerouting for Fault Reconfiguration in Field Programmable Gate Arrays, IEEE, 1999.
Ginetti et al., Modifying The Netlist After Placement for Peformance Improvement, IEEE 1993.
Stenz et al., Timing Driven Placement in Interaction with Netlist Transformations, ACM 1997.
Benkoski et al., The Role of Timing Verificaiton in Layout Synthesis, ACM 1991.
Donath et al., Transformation Placement and Synthesis, IEEE 2000.

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