Cell library generating method and apparatus

Details Cell library generating method and apparatus Cell library generating method and apparatus

1997-03-04

2000-03-07

Teska, Kevin J.

G06F 1750

Patent

active

060351128

ABSTRACT:
A method and apparatus for generating a library for use in a logic simulator. The library includes information on a plurality of cells whose functions are expressed in accordance with a truth table model by combining patterns of input signals and output signals. Information on each cell is input to the logic simulator. It is determined if an input signal to each cell includes an edge signal indicative of rising or falling of that input signal. When the input signal includes the edge signal, the pattern is selected. The selected pattern is then separated from the truth table model of the cell and is developed into two patterns. The developed two patterns include input signals having different levels according to the edge signal. The remaining and developed patterns are thereafter combined to form a new truth table model to be used in the simulation. When the truth table model has reference to a self-output value, a new table is formed that includes a virtual memory.

REFERENCES:
patent: 5416719 (1995-04-01), Peibitich
Paper by Takamine, Miyamoto, Nagashima, Miyoshi and Kawab titled Clock Event Suppression Algorithm fo Velvet and its Appliation to S-820 Development, 25th ACM/IEEE Design Automation Conference pp 716-719, 1988.

Affiliated with

Also associated with

Rating

Cell library generating method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cell library generating method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cell library generating method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-370833