Cell delay addition circuit

Details Cell delay addition circuit Cell delay addition circuit

1993-07-02

1995-02-28

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, H04L 1256

Patent

active

053943953

ABSTRACT:
A cell delay addition circuit can easily feed any desired delay to each of input cells in a communication apparatus or the like for asynchronous transfer mode operation. A time stamp is obtained for an inputted cell based on a sum of a delay amount from a delay amount producing circuit and the current time produced by a clock circuit. The time stamp and the input cell are written in a cell buffer. On the reading side, a comparator reads out a time stamp from the cell buffer and when the comparator detects that the current time tm is equal to or greater than the time stamp, the comparator produces a cell output enable signal ce so that the cell buffer produces the cell.

REFERENCES:
patent: 4255814 (1981-03-01), Osborn
patent: 4271483 (1981-06-01), Baldwin et al.
patent: 4894823 (1990-01-01), Adelmann et al.
patent: 5127000 (1992-06-01), Henrion
patent: 5138637 (1992-08-01), Fox

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