Cell characteristic measuring circuit for a nonvolatile semicond

Details Cell characteristic measuring circuit for a nonvolatile semicond Cell characteristic measuring circuit for a nonvolatile semicond

1995-08-09

1997-07-22

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518511, 36518505, G11C 1134

Patent

active

056509618

ABSTRACT:
A cell characteristic measuring circuit for a nonvolatile memory is provided which, with the use of one circuit can satisfy both the requirements necessary to a characteristic evaluation using a cell array TEG and reliability evaluation using a memory circuit. The measuring circuit comprises a cell array having a matrix array of NAND strings each having a plurality of series-connected cell transistors, a first select gate and a second select gate connected in series. The cell array is divided into a plurality of blocks, a select gate line is connected to the gates of first select gates in each NAND string in the same block, and a word line is connected to the control gates of cell transistors in each row. A first external terminal is connected to a selected bit line, and a second external terminal is connected to each word line in the plurality of blocks.

REFERENCES:
patent: 5247480 (1993-09-01), Itoh et al.
patent: 5253206 (1993-10-01), Tanaka et al.
patent: 5379256 (1995-01-01), Tanaka et al.
C. Dunn, et al. "Flash EEPROM Disturb Mechanisms," Proceedings of 1994 IEEE/IRPS, pp. 299-308.
D.M. Hoffstetter et al. "A Systematic Test Methodology For Identifying Defect-Related Failure Mechanisms in an EEPROM Technology," Proceedings of IEEE 1994 Int. Conference on Microelectronic Test Structures, vol. 7, Mar. 1994, pp. 114-118.

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