Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2007-03-27
2007-03-27
Nguyen, Chau (Department: 2616)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S428000, C370S351000, C370S389000
Reexamination Certificate
active
09870841
ABSTRACT:
A router includes a routing layer and a switching layer. The routing layer includes a plurality of I/O ports for exchanging data with components external to the router. The switching layer is adapted to switch data packets between I/O ports of the routing layer. The switching layer includes an array of cells in communication with the routing layer for permitting exchange of data packets between the array of cells and the routing layer. Each cell includes a memory for receiving a data packet from the routing layer. The routing layer includes a controller to control release of a data packet toward a cell of the array at least in part on a basis of a degree of occupancy of the memory in the cell.
REFERENCES:
patent: 4849751 (1989-07-01), Barber et al.
patent: 4955020 (1990-09-01), Stone et al.
patent: 5008878 (1991-04-01), Ahmadi et al.
patent: 5043980 (1991-08-01), Day, Jr. et al.
patent: 5072366 (1991-12-01), Simcoe
patent: 5189672 (1993-02-01), Le Bihan
patent: 5247513 (1993-09-01), Henrion et al.
patent: 5278548 (1994-01-01), Haber
patent: RE34755 (1994-10-01), Eng et al.
patent: RE34811 (1994-12-01), Eng et al.
patent: 5377182 (1994-12-01), Monacos
patent: 5408469 (1995-04-01), Opher et al.
patent: 5467347 (1995-11-01), Petersen
patent: 5787084 (1998-07-01), Hoang et al.
patent: 5790539 (1998-08-01), Chao et al.
patent: 5831980 (1998-11-01), Varma et al.
patent: 5859835 (1999-01-01), Varma et al.
patent: 5926482 (1999-07-01), Christie et al.
patent: 5938736 (1999-08-01), Muller et al.
patent: 5999527 (1999-12-01), Petersen
patent: 6052373 (2000-04-01), Lau
patent: 6069895 (2000-05-01), Ayandeh
patent: 6111856 (2000-08-01), Huterer et al.
patent: 6115378 (2000-09-01), Hendel et al.
patent: 6134217 (2000-10-01), Stiliadis et al.
patent: 6134218 (2000-10-01), Holden
patent: 6144662 (2000-11-01), Colmant et al.
patent: 6157643 (2000-12-01), Ma
patent: 6424659 (2002-07-01), Viswanadham et al.
patent: 6560629 (2003-05-01), Harris
patent: 6597689 (2003-07-01), Chiu et al.
patent: 6611519 (2003-08-01), Howe
patent: 6687254 (2004-02-01), Ho et al.
patent: 6731631 (2004-05-01), Chang et al.
patent: 6735173 (2004-05-01), Lenoski et al.
patent: 6741552 (2004-05-01), McCrosky et al.
patent: 6751562 (2004-06-01), Blackett et al.
patent: 6754206 (2004-06-01), Nattkemper et al.
patent: 6754216 (2004-06-01), Wong et al.
patent: 6778529 (2004-08-01), Field et al.
patent: 6778534 (2004-08-01), Tal et al.
patent: 6804731 (2004-10-01), Chang et al.
patent: 6807167 (2004-10-01), Chakrabarti et al.
patent: 6907042 (2005-06-01), Oguchi
patent: 6909716 (2005-06-01), Johnson et al.
patent: 6940814 (2005-09-01), Hoffman
patent: 0 241 152 (1987-10-01), None
patent: 0 680 173 (1995-02-01), None
patent: 1 051 001 (2000-11-01), None
patent: WO 98/26539 (1998-06-01), None
US 5,361,257, 11/1994, Petersen (withdrawn)
Werner Bux et al.; Technologies and Building Blocks for Fast Packet Forwarding; IEEE Communications Magazine; Jan. 2001; pp. 70-77.
Minagawa, N. et al. ; Dept. of Comput. Scil, University of Electro-Commun. Tokyo, Japan; Implementation of a network switch on chips;(Abstract) Communications, vol. 13, No. 1; retrieved on Mar. 16, 2001 from INSPEC database.
Saturn: a terabit packet switch using dual round-robin; (abstract) Globecom'00—IEEE, Global Telecommunications Conference; Dept. of Electr. Eng. Polytech, Univ.of Brooklyn, NY, U.S.A.; retrieved on Jun. 4, 2001 from INSPEC database.
Nanette J. Boden et al.; Myrinet—Gigabit-per-Second Local-Area Network [on line]; Nov. 16, 1994 Myricom, Inc.; Internet URL http;//www.myrinet.com/research/publications/Hot.ps; retrieved on Mar. 14, 2001.
Vitesse Semiconductor Corporation [on line] ; Datasheet VSC880; Jan. 5, 2001; pp. 1-20; retrieved on Jul. 23, 2001; Internet URL www.vitesse.com/products/documents.cfm.family= document-id=180.
Vitesse Semiconductor Corporation [on line] ; Datasheet VSC870; Jun. 29, 2001; pp. 1-40; retrieved Jul. 23, 2001; Internet URL www.vitesse.com.
A New Architecture for Switch and Router Design: PMC-Sierra Inc.; Dec. 22, 1999; Internet URL http://www.pmcsierra.com/pressRoom/pht/1cs—wp.pdf retrieved on Jul. 4, 2001; pp. 1-8.
Network Processor Designs for Next-Generation Networking Equipment [on line ] ; EZ Chip Technologies; Internet URL http://www.ezchip.com/images/pdfs/etchip—white—paper.pdf; retrieved on Jul. 4, 2001; Dec. 1999; pp. 1-4.
Cyrel Minkenberg et al. A combined Input an dOutput Queued Packet-Switched System Based on Prizma Switch-on-a-Chip Technology; Scalable High-Speed Switches/Routers with QoS Support; IBM Research, Zurich Research Laboratory; IEEE Communications Magazines; Dec. 2000; pp. 70-84.
Werner Bux et al.; Technologies an d Building Blocks for Fast Packet Forwarding; Telecommunications Networking at the Start of the 21st Century; IEEE Communications Magazine; Jan. 2001; pp. 70-77.
Child, J.; Bus-switching chip busts bandwidth barrier [on line ] ; Internet URL http://www.computer-design.com/editorial/1995/06/directions/bus.html; retrieved on Mar. 15, 2001.
PSID—Based Communications Switching [on line ] ; Dec. 1997; Internet URL http://www.icube.com/commsw.pdf; retrieved on Mar. 15, 2001; pp. 1-4.
Nick McKeown et al. “The Tiny Tera: a Packet Switch Core”; Departments of Electrical Engineering and Computer Science, Stanford University; Aug. 1996; http://tiny-tera.stanford.edu/tiny-tera/index.htwl.
Notani H et al: “An 8*8 ATM switch LSI with shared multi-buffer architecture” Proceedings of the Symposium on VLSI Circuits, Seattle, Jun. 4-6, 1992, Symposium on VLSI Circuits, New York, IEEE, US, Jun. 4, 1992, pp. 74-75, XP010064987.
International Search Report PCT/CA02/00810, Aug. 1, 2003.
French, R., Architectural Consideration for Internet Reuters; retrieved from the internet guideline in file; Internet URL www.cise.ufl.edu/ rfrench, accessed Jul. 23, 2001.
Joseph Desposito; Router-On-A-Chip Manages Network Traffic with Wire-Speed QoS; Electronic Design; May 1, 2000; pp. 64-65-66.
Partial International Search; PCT/CA02/00810.
Cote Sebastien
De Maria Marcelo
Langlois Carl
Norman Richard S.
4198638 Canada Inc.
Lee Andrew C.
Nguyen Chau
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