Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2000-03-13
2002-06-04
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S202000, C257S203000
Reexamination Certificate
active
06399972
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to cell based integrated circuits and unit cell architecture for such circuits, which result in significant improvement of the degree of integration.
BACKGROUND OF THE INVENTION
Cell based integrated circuit technology and cell architecture for such circuits have been developed as quick-turns integrated circuit (IC) design methodologies in which pre-designed circuit units or cells are wired together to rapidly implement a new IC functionality. The pre-designed circuit elements are called macro cells which are made by interconnecting unit cells.
A conventional unit cell includes a P-type active region (PMOS transistor) and an N-type active region (NMOS transistor), which are arranged in a first direction. A pair of poly-silicon regions is formed on each of the P-type and N-type active regions. Those poly-silicon regions are extending in parallel to each other in the first direction. The unit cell also includes first and. second substrate contact regions, which are arranged in parallel to the P-type active region and N-type active region respectively.
When a circuit, such as a macrolibrary, is made, the poly-silicon regions on the P-type active region are connected to the poly-silicon regions on the N-type active region with conductive lines.
According to the conventional unit cell, power line (Vdd) and ground line (Vss) across the P-type active region and N-type active region; therefore the arrangement of conductive lines becomes complicated. To prevent intersection between signal lines and power line/ground line, the signal lines should be formed on a different layer from the power line and ground line. As a result, it becomes difficult to increase the degree of integration of the IC.
Further, conductive lines connecting the poly-silicon lines on the P-type active region and N-type active regions may across the signal lines, therefore the arrangement of conductive lines becomes complicated. To prevent intersection between such conductive lines and the signal lines, the signal lines should be formed on a different layer. As a result, it becomes difficult to increase the degree of integration of the IC.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for designing a unit cell that contributes for increasing the degree of integration of the integrated circuit.
Another object of the present invention is to provide a unit cell that contributes for increasing the degree of integration of the integrated circuit.
Further object of the present invention is to provide an integrated circuit of which the degree of integration can be increased.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, in a method for designing a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions are arranged to extend in a first direction. Each of the active regions has first and second ends thereof. The first end of the second conductive type active regions is opposing to the second end of the first conductive type active region. In the method, a poly-silicon pattern is provided to extend in the first direction across the first conductive type active region and second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.
Preferably, the first conductive type active region is formed to have a projecting region at the first end, which extends in the first direction toward the first contact region; and the second conductive type active region is formed to have a projecting region at the second end, which extends in the first direction toward the second contact region.
The poly-silicon pattern may extend in, the first direction continuously without any break therein.
According to a second aspect of the present invention, a unit cell that is designed by a method according to the above described first aspect of the present invention.
According to a third aspect of the present invention, an integrated circuit that is made by a unit cell according to the above described second aspect of the present invention.
REFERENCES:
patent: 4516312 (1985-05-01), Tomita
patent: 4595940 (1986-06-01), Gandini
patent: 4750026 (1988-06-01), Kuninobu et al.
patent: 5898194 (1999-04-01), Gheewala
patent: 57-45948 (1982-03-01), None
patent: 1-274450 (1989-11-01), None
Ishikawa Hirokazu
Masuda Hirohisa
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
Wilson Allan R.
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