Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1998-09-30
2001-01-23
Picard, Leo P. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S206000, C257S207000, C257S208000, C257S390000
Reexamination Certificate
active
06177691
ABSTRACT:
FIELD OF THE INVENTION
This application relates to designs for cell based arrays, and particularly relates to low power, high density designs for cell based arrays.
BACKGROUND OF THE INVENTION
The use of gate arrays and standard cells has become well known as an effective and efficient method for rapidly developing new semiconductor products of substantial complexity. Such standard cells are typically used in cell-based arrays, and have wide application within the industry. A widely-accepted design for a gate array architecture that provides standard cell type densities is based on the design described in U.S. Pat. No. 5,289,021, commonly assigned to the assignee of the present invention and incorporated herein by reference.
However, despite the many advantages offered by cell based arrays, prior art designs cells have suffered from some limitations which have become more apparent as line widths have been reduced and complexity has increased. In particular, the typical prior art gate array has been limited to a relatively low ratio between compute and drive cells. More specifically, prior art designs have limited the ratio between compute and drive cells to no more than three- or four-to-one. Moreover, manufacturing limitations have served to impose a fixed, three-to-one limitation on most if not all prior art designs. Although the three-to-one ratio has enabled efficient construction of a great many circuits, and is particularly well suited to many high performance designs, there remain other applications—for example, low power applications—which could benefit from a ratio of compute to drive cells other than (and typically greater than) three-to-one.
As a result, there has been a need to develop a cell based array design which permits the implementation of larger, and in some instances unlimited, ratios of compute to drive cells. In addition, there has been a need to develop an improved power routing system to permit most efficient use of the increased density available with these larger ratios.
SUMMARY OF THE INVENTION
The present invention substantially overcomes the limitations of the prior art by providing an extremely compact cell based array which permits high density, low power designs, including permitting designs implementing a virtually unlimited range of ratios between compute and drive cells. In particular, the present invention involves providing design flexibility to permit the ratio of compute cells to drive cells to be design dependent, and therefor optimized for each particular design. Because of the substantially larger size of the drive cell transistors compared to the compute cell transistors, increasing ratios of compute to drive cells offers significant reduction in power consumption, among other benefits. Further, higher densities can result for designs with high C/D ratios. While the structure is typically implemented as a gate array, many aspects of the invention also have application in standard cell designs. As a result, the present invention is not limited to gate arrays, and reference herein will be made to both types of structures even though the exemplary embodiment is typically a gate array.
The cell based array of the present invention involves a new and novel cell structure which involves rearrangement of the compute cells relative to each other and to any associated drive cells, with the objectives of providing, among other things, lower power, higher density operation with greater optimization. To achieve these goals, an exemplary embodiment of the present invention includes adding a substrate tap to the compute cell and arranging adjacent compute cells to permit the substrate tap to be shared between adjacent compute cells. Further, although optional, the n-well taps preferably abut between adjacent compute cells.
In contrast to the compute cells, however, in at least some embodiments the well and substrate taps are preferably removed from the drive cell. Still further, in at least a presently preferred embodiment the source/drain areas of the transistors for adjacent drive cells is separated, thereby improving routability by providing an extra routing track between the drive cells. In addition, flexibility is improved because the two cells need not be connected.
Still further, additional performance gains may be provided by, in at least some embodiments, adding additional polysilicon heads to the drive cell while at the same time minimizing the number of bent gates to effectively increase channel width of the drive cell's PMOS device.
In addition, another aspect of the present invention includes a power mesh of an arrangement of criss-crossing power rings which surround the core and are supplied power from the VDD and GND I/O pads. In turn the power rings supply VDD and GND to the core through a Primary as well as a Supplemental Power mesh as discussed hereinafter. This provides the design with the flexibility to support a wide range of C:D ratios, and particularly a range of C:D ratios from 3 to 13 although a broader range is within the scope of the invention. The power mesh design, taken together with the broad range of C:D ratios, allows users to gain maximum density advantage from the architecture.
The power mesh, or power routing scheme, is implemented in a two-tiered arrangement. Primary power routing is provided by means of two conductive layers arranged in the horizontal direction, plus an additional layer in the vertical direction. Optional secondary or supplemental power routing is by a fourth conductive layer in the vertical direction, plus the horizontal portion of the primary conductive layer can be supplemented by an overlying conductive layer in the same direction. The conductive layer typically, but not necessarily, is a metal layer. Also, the CBAII core cells have been designed with at least one n-well & substrate contact each inside every cell to avoid latchup problems.
The invention is particularly well-suited to complex integrated circuits such as cell-based arrays, but may be successfully implemented in a wide variety of circuit designs. Although the invention is explained in the context of a cell-based array, it is to be understood that such an embodiment is exemplary only and not limiting. Likewise, the power mesh described here is exemplary only and may be implemented in a variety of designs.
The foregoing and other advantages of the present invention may be better appreciated from the following Detailed Description of the Invention, taken together with the attached Figures.
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Iranmanesh Ali Akbar
Sawhney Puneet
Duong Hung Van
Eakin James E.
McDermott & Will & Emery
Picard Leo P.
Synopsys Inc.
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