Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1997-12-04
2001-01-09
Olms, Douglas W. (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S229000
Reexamination Certificate
active
06172979
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to (Cell Delay Variation) CDV-reducing algorithm circuit self-monitoring systems in shaping function systems.
It is well known in the art that an ATM network should have a commonly termed shaping function to alleviate a burst character causing reduction of its utility. The shaping function has resort to a CDV-reducing algorithm. CDV-reducing algorithms are realized by hardware logic circuits. Hereinunder, such a hardware logic circuit is referred to as CDV-reducing algorithm circuit.
In a CDV-reducing algorithm circuit, the transmission time, i.e., instant of transmission, of an input cell is determined from minimum inter-cell interval T
s
, permissible residual CDV &tgr;
s
, cell arrival time ta, theoretical next cell transmission time TET under shaping function, ideal cell transmission time t
o
derived from shaping and arrival time of a cell immediately proceeding the VP of the input cell, and written in a shaping buffer at a position thereof corresponding theretoto.
FIG. 4
is a flow chart illustrating a process in a CDV-reducing algorithm circuit. In a step
11
, initial parameter data (T
s
, &tgr;
s
, TET=t
a
and t
o
=t
a
) are set. When the arrival of a cell at time t
s
is detected in a step
12
, parameter data corresponding to VPI (VCI) is read out in a step
13
, and then a step
14
is executed.
In the step
14
, a check is made as to whether the detected arrival cell is a user's cell or a non-user's cell. In the case of a user's cell, a step
15
is executed, in which a check is made as to whether theoretical cell transmission time TET is greater than the sum of cell arrival time t
s
and permissible residual CDV &tgr;
s
. In the case when the arrival cell is a non-user's cell, an operation which will be described late is brought about.
When the theoretical cell transmission time TET is not greater than the sum of the cell arrival time t
a
and the permissible residual CDV time &tgr;
s
, a step
16
is executed, in which the theoretical cell transmission time TET is set to a predetermined time, i.e., max (t
a
, TET). Then, in a step
17
an ideal cell transmission time t
o
is set to the cell arrival time t
a
, and then a step
18
is executed.
When the theoretical cell transmission time TET is greater than the sum of the cell arrival time t
s
and the permissible residual CDV &tgr;
s
, the routine goes to a step
19
, in which the ideal cell transmission time to is set to the sum of the theoretical cell transmission time TET and the permissible residual CDV &tgr;
s
, and then the step
18
is executed. In the step
18
, the theoretical cell transmission time TET is updated by minimum cell time Ts.
When it is found in the step
14
that the arrival cell is a non-user's cell, the routine goes to a step
110
, in which the time relation between the ideal cell transmission time T
a
and the cell arrival time t
a
is checked. When the cell arrival time t
a
is found to be later than the ideal cell transmission time t
o
, a step
111
is executed, in which the ideal cell transmission time t
o
is set to the cell arrival time t
a
, and then a step
112
is executed. When the cell arrival time t
a
is found to be earlier than the ideal cell transmission time t
o
, a step
112
is executed. In the step
112
, the ideal cell transmission time is set t
o
, and the routine goes back to the step
12
.
The CDV-reducing algorithm circuit as described above with reference to the flow chart of
FIG. 4
, has five different operation patterns #
1
to #
5
as shown in FIG.
5
. These operation patterns #
1
to #
5
are labeled as #
1
to #
5
in the flow chart of FIG.
4
.
The above CDV-reducing algorithm circuit can guarantee an ideal cell transmission interval to a certain extent.
However, when an abnormal operation result is produced, which is attributable to hardware of the CDV-reducing algorithm circuit, accurate shaping becomes impossible. Accordingly, it is necessary to provide a mechanism, which can detect an abnormality as soon as the occurrence thereof, and producing an alarm for early removal of the abnormality and restoration of the circuit. In addition, it is necessary to detect an abnormality without interrupting the shaping operation but in an in-service state of the circuit.
SUMMARY OF THE INVENTION
An object of the invention therefore is to provide a reduced CDV algorithm circuit self-monitoring system, which detects an abnormal operation attributable to hardware of a CDV-reducing algorithm circuit and provides an alarm as soon as the occurrence thereof.
According to the invention, there is provided a CDV-reducing algorithm circuit self-monitoring system operative for detecting a non-data cell contained in a cell flow and arriving at a predictable time, executing a CDV-reducing algorithm operation on the detected non-data cell using self-monitoring parameters, comparing the result of the reduced CDV algorithm operation and an estimated value, and determining, when the two compared data are equal, that the CDV-reducing algorithm is normal, while making, when the two compared data fail to be equal, a determination that the CDV-reducing algorithm is abnormal and also notification of an alarm to a function control system.
The non-data cell arrives periodically and the arrival time instant of the non-data cell is measurale on the basis of a certain function.
According to another aspect of the present invention, there is provided a CDV-reducing algorithm circuit self-monitoring system for a CDV-reducing algorithm circuit having five different operation patterns, i.e., one of shaping in which t
o
is set to t
o
=TET−&tgr;
s
, one in which t
o
is set to t
o
=t
a
with TET unchanged, one in which t
o
is set to t
o
=t
a
with new TET, one in which a bypass executed under t
o
>t
a
, and one in which an update or a baypass is executed such that t
o
=t
s
under t
o
<t
a
, the CDV-reducing algorithm circuit self-monitoring system being operative for defining a self-monitoring pattern t
o
(k) (k being 0, . . . 4), executing a normal policing operation on an arrival cell other than periodic cells and, upon detection of a periodic cell, reading out t
o
(i) and predetermined self-monitoring parameter data TET (TET(i)) for k=i to make a theoretical value as a CVD-reducing algorithm operation result equal to t
o
(i), executing a CDV-reducing algorithm operation by using TET(i) in lieu of TET at the theoretical periodic cell transmission time, comparing the operation result t
o
and t
o
(i), and determining, when the two compared data are equal, that the CDV-reducing algorithm is normal, while making, when the two compared data fail to be equal, a determination that the CDV-reducing algorithm is abnormal and also notification of an alarm to a function control system.
According to further aspect of the present invention, there is provided a CDV-reducing algorithm circuit self-monitoring apparatus comprising means for detecting non-data cells contained in a cell flow and arriving at predictable times, means for a CDV-reducing algorithm operation on each detected non-data cell by using self-monitoring parameters, means for comparing the result of the CDV-reducing algorithm operation and an estimated value and determining, when the two compared data are equal, that the CDV-reducing algorithm is normal, while making, when the two compared data fail to be equal, a determination that the CDV-reducing algorithm is abnormal and also making notification of an alarm to a function control system.
Other objects and features will be clarified from the following description with reference to attached drawings.
REFERENCES:
patent: 5274641 (1993-12-01), Shobatake
patent: 5581545 (1996-12-01), Morimoto
patent: 5668797 (1997-09-01), Fahmi
patent: 5694554 (1997-12-01), Kawabata
patent: 5751695 (1998-05-01), Ohashi
patent: 3-241944 (1991-10-01), None
patent: 4-25255 (1992-01-01), None
patent: 4-46432 (1992-02-01), None
patent: 4-100451
McGuireWoods LLP
NEC Corporation
Olms Douglas W.
Pizarro Ricardo M.
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