CDR algorithms for improved high speed IO performance

Details CDR algorithms for improved high speed IO performance CDR algorithms for improved high speed IO performance

2005-08-23

2009-06-30

Odom, Curtis B (Department: 2611)

Pulse or digital communications

Synchronizers

C375S373000, C375S375000, C375S376000, C327S156000, C327S160000

Reexamination Certificate

active

07555085

ABSTRACT:
A data receiver system. The system includes a clock generator configured to output a reference clock and circuitry configured to measure a direction of a phase difference between an input data stream and the reference clock. The circuitry is further configured to increment a counter if the phase difference is in a first direction, decrement the counter if the phase difference is in a direction opposite to the first direction, and convey a phase correction signal to the clock generator if an output value of the counter meets or exceeds a threshold. The clock generator is configured to adjust the phase of the reference clock in response to receiving the phase correction signal.

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“Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems”; Richard C. Walker, Agilent Laboratories, Palo Alto, CA; pp. 1-2.
“A Second-Order Semi-Digital Clock Recovery Circuit Based on Injection Locking”; M.-J. Edward Lee, William J. Dally, John Poulton, Trey Greer, John Edmondson, Ramin Farjad-Rad, Hiok-Tiaq Ng, Rohit Rathi, and Ramesh Senthinathan; Vilio Communications, Milpitas, CA & Stanford University, Stanford, CA; ISSCC 2003/Session 4/Clock Recovery and Backplane Transceivers/ Paper 4.3; © 2003 IEEE International Solid-State Circuits Conference.
“Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems”; Richard C. Walker, Agilent Laboratories, Palo Alto, CA; pp. 1-12, IEEE Press, Feb. 2003.

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