CDMA receiver comprising a synchronous timing notifying...

Multiplex communications – Communication over free space – Signaling for performing battery saving

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C455S574000

Reexamination Certificate

active

06574200

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a receiver which is intermittently operable and, more particularly, to a technique which can make a code division multiple access (CDMA) receiver intermittently carry out reception operation.
Recently, development of a mobile communication system is remarkable and there have been strong demands in the fields of mobile communication terminals for use in the mobile communication system. In general, each of the mobile communication terminals of the type described in driven by a battery which has a finite lifetime. Accordingly, in order to extend a use time in the mobile communication terminal without replacement of the battery frequently, it is necessary to remove consumption of useless current in the mobile communication terminals as much as possible. As such technique, in a case where the mobile communication terminal is put into a wait state, a method of making the mobile communication terminal operate intermittently is adapted.
In a case where this intermittent operation is realized in a spread spectrum technique such as the code division multiple access (CDMA), attentions will be made as regards points which will presently be described.
In general, it is known as characteristics in the receiver for receiving a spread spectrum received signal such as a CDMA receiver that reception information itself cannot be decoded if a synchronous state between the spread spectrum received signal and a despreading code for use in despreading is strictly matched. In addition, for this purpose, a clock signal used as a reference signal of synchronous timings preferably has a high frequency and is stable.
Those situations are required not during reception but also in a case of making the receiver establish the synchronous state operate intermittently. That is, it is necessary to ensure a correct synchronization between the spread spectrum received signal and the despreading code as rapidly as possible on making the receiver operate intermittently transit from a reception operation stop state to a reception operation state.
Under the circumstances, that is, in consideration of a balance of the above-mentioned low consumption of current and necessity of a rapid synchronous acquisition on transiting from the reception operation stop state to the reception operation state, various conventional methods are already proposed as methods for making the receivers such as the CDMA receivers operate intermittently. The conventional methods are classified into first and second conventional methods as follows.
The first conventional method comprises the step of making only a high-frequency oscillation section operate when operations of other receiving parts stop during the reception operation stop state in an intermittent operation state, thereby holding a synchronous established state. The high-frequency oscillation section comprises a high-frequency oscillator acting as a time reference oscillator for high precision and a high-speed counter for frequency dividing a high frequency signal outputted from the high-frequency oscillator to produce a divide signal. That is, in the first conventional method, the receiver is put into, during the intermittent operation state, a hot standby state where the high-frequency oscillation section operates while the operations of the other receiving parts stop for a reception operation stop time interval of the reception operation stop state.
The second conventional method comprises the step of resetting a phase state of the despreading code whenever the receiver is put into the reception operation state in the intermittent operation state to resynchronize the despreading code to the spread spectrum received signal in accordance with an initial synchronous acquisition procedure. In other words, in the second conventional method, the receiver is put into, during the intermittent operation state, a sleep state where operation of the high-frequency oscillation section stop for the reception operation stop time interval.
Various CDMA receivers of the type are already known. By way of example, Japanese Unexamined Patent Publication of Tokkai No. Hei 5-191,375 or JP-A 5-191375 discloses a spread spectrum system receiving equipment which is capable of execute a synchronous acquisition of a spreading code in a short time at the time of dormant state in an intermittent receiving operation and which is capable of reducing the power consumption. According to JP-A 5-191375, in the case of switching to a dormant state from reception at the time of intermittent receiving operation, a switch is connected to a fixed frequency oscillating circuit, and by driving a local spreading code generating circuit by its free-running clock, a phase difference of a spreading code is prevented from becoming large, the switch is connected to a phase delaying circuit, a phase of a local spreading code generated by the code generating circuit is delayed by a portion of a phase shift of the local spreading code estimated at the time of dormant state, and subsequently, the switch is connected to a phase advancing circuit, so that a phase of an output of the code generating circuit advances little by little, and at the moment a large correlation value is generated in an output of a correlator in such a state, the switch is connected a delay lock loop, and switched to a regular synchronization tracking operation.
Japanese Unexamined Patent Publication of Tokkai No. Hei 7-123,024 or JP-A 7-123024 discloses a method for initial pull-in of automatic frequency control and its receiver in which a time required when initial pull-in of automatic frequency control is made available in a spread spectrum communication. According to JP-A 7-123014, an AFC circuit is composed of a mixer, an A/D converter, a digital matched filter (DMF), an oscillator (OSC), a frequency discriminator, a D/A converter, an AFC control circuit, and a voltage controlled oscillator (VCO). Then, a sample clock frequency outputted from the oscillator is selected to be a frequency higher than or lower than one-chip frequency of a chip clock frequency of a sender side included in a received IF input by about two cycles. Thus, fluctuation in the correlation due to frequency deviation between transmission and reception clock signals is suppressed in a short time and the clock generated from the voltage controlled oscillator is synchronized quickly with the chip clock frequency.
Japanese Unexamined Patent Publication of Tokkai No. Hei 8-321,804 or JP-A 8-321804 discloses a communication terminal equipment.which is capable of considerable reducing power consumption at the time of intermittent reception in the communication terminal equipment. According to JP-A 8-321804, the state value of a second spreading code generation means at the time of next starting is set in a register means and a timer means is operated. Second and first spreading code generation means and a reception system circuit are stopped and a system becomes a sleep state. At the time or restarting by the time-out of the timer means, the reception system circuit is operated and the second spreading code generating means is operated from the state value which is set in the register means. Furthermore, an intermittent reception means operating the first spreading code generation means from an initial state is provided. Thus, the first and second spreading code generation means can be stopped at the time of non-reception, and power consumption at the time of intermittent reception can considerably be reduced.
Japanese Unexamined Patent Publication of Tokkai No. Hei 9-284,151 or JP-A 9-284151 discloses a receiver, a reception method, and a communication system which are capable of keeping the synchronization precision in the standby state and of caving the power consumption. According to JP-A 9-284151, a control circuit applies power supply control or the like to each circuit such as a synchronization correction signal generating circuit, a pseudo-noise (PN) code generator and an information decoding circuit in each independent timing

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

CDMA receiver comprising a synchronous timing notifying... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CDMA receiver comprising a synchronous timing notifying..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CDMA receiver comprising a synchronous timing notifying... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3156973

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.