CDMA receiver

Details CDMA receiver CDMA receiver

1999-07-07

2003-01-14

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S152000, C370S342000

Reexamination Certificate

active

06507603

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a CDMA receiver and, more particularly, to a CDMA receiver for receiving a signal containing data that has been spread by a predetermined spreading code sequence, calculating a correlation value between a reference code sequence and a spread data sequence obtained by sampling the received signal at a predetermined sampling rate, and adopting, as despread start timing, the timing at which the correlation value is maximized.
Competition to develop ever smaller terminals in the field of modern mobile communications is intense and there is a need to reduce the power consumed by these terminals.
Digital cellular wireless communication systems using DS-CDMA (Direct-Sequence Code Division Multiple-Access) technology have been developed as next-generation mobile communication systems for implementing wireless multimedia communication. In a CDMA digital cellular wireless communications system of this kind, a base station transmits control information and user information upon multiplexing the information with a spreading code. Individual mobile stations receive the control information from the base station, spread the transmission information using a spreading code specified by the base station and then send the information. By accepting this control information, each mobile station is capable of performing a variety of control operations. For example, the mobile station performs position registration and acquisition of information concerning base stations in the area and carries out control for call origination and incomingcall standby. In order for a mobile station to receive control information from the base station in a CDMA digital cellular wireless communications system of this kind, it is necessary to identify the start timing (phase) of spread data that has undergone spread-spectrum modulation.
FIG. 13
is a diagram showing the construction of a CDMA transmitter in a base station device which sends transmission data of control and user channels upon code-multiplexing the data. The transmitter includes spread-spectrum modulators
11
1
-
11
n
of respective control/user channels, each having a frame generator
21
, a serial/parallel (S/P) converter
22
for converting frame data to parallel data, and a spreading circuit
23
. The frame generator
21
includes a transmission data generator
21
a
for generating serial transmission data D
1
, a pilot signal generator
21
b
for generating a pilot signal P, and a framing circuit
21
c
for forming the serial data D
1
into blocks a prescribed number of bits at a time and inserting the pilot signal P before and after every block to thereby form frames. The pilot signal, when all “1”s, for example, allows the receiver to recognize the amount of phase rotation caused by transmission so that the data may be subjected to a phase rotation of an equivalent amount in the opposite direction.
The S/P converter
22
alternately distributes the frame data (the pilot signals and transmission data) one bit at a time to convert the frame data to I-component (in-phase component) data D
I
and Q-component (quadrature-component) data D
Q
.
The spreading circuit
23
includes a pn sequence generator
23
a
for generating a pn sequence (long code) specific to the base station, an orthogonal Gold code generator
23
b
for generating an orthogonal Gold code (short code) specific to the control channel and user channel, an EX-OR gate
23
c
for outputting a spreading code C
1
by taking the exclusive-OR between the long code and the short code, and EX-OR gates
23
d,
23
e
for performing spread-spectrum modulation by taking the exclusive-ORs between the data D
I
and D
Q
(symbols) respectively, and the spreading code C
1
. It should be noted that since “1” is level −1 and “0” is level +1, the exclusive-OR between signals is the same as the product between them.
Also shown in
FIG. 13
are a combiner
12
i
for outputting an I-component code-multiplexed signal &Sgr;V
I
by combining the I-component spread-spectrum modulated signals V
I
output by the respective spread-spectrum modulators
11
1
~
11
n
of the user channel; a combiner
12
q
for outputting a Q-component code-multiplexed signal &Sgr;V
Q
by combining the Q-component spread-spectrum modulated signals V
Q
output by the respective spread-spectrum modulators
11
1
~
11
n
; FIR-type chip shaping filters
13
i,
13
q
for limiting the bandwidths of the code-multiplexed signals &Sgr;V
I
, &Sgr;V
Q
, respectively; DA converters
14
i,
14
q
for converting the analog outputs of the respective filters
13
i,
13
q
to analog signals; a quadrature modulator
15
for applying quadrature phase-shift keying (QPSK) modulation to the code-multiplexed signals &Sgr;V
I
, &Sgr;V
Q
of the I and Q components and outputting the modulated signal; a transmitting circuit
16
for converting the output signal frequency of the quadrature modulator to a radio frequency, applying high-frequency amplification and then outputting the signal, and an antenna
17
.
FIG. 14
is a diagram illustrating the construction of the receiver of a mobile station. The receiver includes an antenna
21
; a receiver circuit
22
for performing amplification and frequency conversion from RF (radio frequency) to IF (intermediate frequency); a QPSK detector
23
for performing QPSK detection and outputting I, Q signals; an AD converter
24
for converting baseband analog I, Q signals, which are the detector outputs, to digital I, Q data, respectively; a despreading circuit
25
for performing despreading by multiplying the I, Q data by a spreading code sequence identical with that of the base station; a data demodulator
26
for performing synchronous detection, data discrimination and error correction; and a searcher
27
.
The searcher
27
has a matched filter
31
for performing correlation, a timing identification unit
32
for identifying spread start timing (phase), and a code table
33
for generating a reference code sequence. The matched filter
31
performs a correlation operation between a received spread data sequence and the reference code sequence in order to identify the despread start timing. The timing identification unit
32
acquires the spread start timing (phase) based upon the timing at which a correlation value between the received spread data sequence and the reference code sequence exceeds a set level.
FIG. 15
is a diagram useful in describing the structure of the matched filter and a method of specifying despread timing. The matched filter
31
includes an (n+1)-chip shift register (s
0
-S
n
)
31
a
for successively shifting a spread data sequence of the baseband at the chip frequency f
c
; an (n+1)-chip shift register (c
0
-c
n
)
31
b
for storing the spreading code sequence, which is the reference code sequence, at the chip frequency; (n+1)-number of multipliers (MP
0
-MP
n
)
31
c
for multiplying corresponding bits of the baseband spread data sequence and reference code sequence; and an adder circuit
31
d
for adding the outputs of the multipliers.
When the correlation between the received spread data sequence and reference code sequence is calculated by the matched filter (MF)
31
, the correlation value becomes large at the moment the spread data sequence and reference code sequence coincide. Accordingly, the timing identification unit
32
monitors the correlation value output by the matched filter
31
, identifies the moment the correlation value exceeds the set level as being the despread start timing and outputs a signal indicative of this.
The foregoing relates to a case where the input to the shift register
31
a
is a spread data sequence obtained by sampling the output signal of the quadrature detector
23
(
FIG. 14
) at the chip frequency f
c
and converting this analog signal to digital data. A single correlation value is obtained per chip. However, if the sampling frequency is made high, a plurality of correlation values can be obtained per chip.
FIG. 16
is a diagram for describing the results of simulation in

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