CDMA power amplifier design for low and high power modes

Details CDMA power amplifier design for low and high power modes CDMA power amplifier design for low and high power modes

2007-04-06

2008-10-28

Nguyen, Khanh V (Department: 2817)

Amplifiers

Combined with automatic amplifier disabling switch means

C330S129000, C330S302000, C330S310000

Reexamination Certificate

active

07443236

ABSTRACT:
An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.

REFERENCES:
patent: 5060294 (1991-10-01), Schwent et al.
patent: 5423074 (1995-06-01), Dent
patent: 6522201 (2003-02-01), Hsiao et al.
patent: 6680652 (2004-01-01), Hoheisel et al.
patent: 6724255 (2004-04-01), Kee et al.

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