CDMA power amplifier design for low and high power modes

Details CDMA power amplifier design for low and high power modes CDMA power amplifier design for low and high power modes

2007-04-10

2007-04-10

Nguyen, Khanh Van (Department: 2817)

Amplifiers

With control of power supply or bias voltage

With control of input electrode or gain control electrode bias

C330S051000, C330S302000, C330S310000

Reexamination Certificate

active

10807764

ABSTRACT:
An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.

REFERENCES:
patent: 5774017 (1998-06-01), Adar
patent: 6188877 (2001-02-01), Boesch et al.
patent: 6215359 (2001-04-01), Peckham et al.
patent: 6297694 (2001-10-01), Yamamoto
patent: 6522201 (2003-02-01), Hsiao et al.
patent: 6784748 (2004-08-01), Canyon et al.
Christopher B. Haskins, “Diode Predistortion Linearization for Power Amplifier RFICs in Digital Radios,” thesis for Master of Science in Electrical Engineering, Virginia Polytechnic Institute and State University, Apr. 17, 2000.

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