CCD stack memory organization

Details CCD stack memory organization CCD stack memory organization

1974-06-21

1976-03-02

Fears, Terrell W.

Communications: electrical

Digital comparator systems

3401725, G11C 1300

Patent

active

039421635

ABSTRACT:
A stack memory having a last-in-first-out memory organization comprising a plurality of pairs of two-phase charge coupled device shift registers arranged into a plurality of rows, the CCD registers of each pair being interconnected by digital logic to provide a circular shift register cell and to direct data into and out of the cell. Each cell is interconnected through its logic to an adjacent cell within the same row, and each row of a plurality of circular shift register cells is interconnected between an input buffer register and an output buffer register. The input buffer register is used to write data into each one of the plurality of rows of cells, and the output buffer register is used to retrieve the data from each row of cells. A system control is included for controlling the read, write, and idle operations, wherein a CCD circular shift register cell provides a control loop for maintaining synchronization over the memory system, and wherein there is also provided a clock generator and switch means for generating clock signals.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 3772658 (1973-11-01), Sarlo

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