CCD imager analog processor systems and methods

Television – Camera – system and detail – With electronic viewfinder or display monitor

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C348S222100, C348S572000, C341S161000

Reexamination Certificate

active

10820577

ABSTRACT:
A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.

REFERENCES:
patent: 6252536 (2001-06-01), Johnson et al.
patent: 6285309 (2001-09-01), Yu
patent: 6340944 (2002-01-01), Chang et al.
patent: 6532370 (2003-03-01), Underbrink et al.
patent: 6617934 (2003-09-01), Holberg et al.
patent: 6686957 (2004-02-01), Johnson et al.
patent: 6707492 (2004-03-01), Itani
patent: 6980148 (2005-12-01), Bahai
patent: 7009548 (2006-03-01), Chiang et al.
patent: 7068319 (2006-06-01), Barna et al.
patent: 7205923 (2007-04-01), Bahai
patent: 2004/0125008 (2004-07-01), Yamaji
patent: 2005/0068218 (2005-03-01), Kobayashi et al.
Kwok et al.; “Power Optimization for Pipeline Analog-to-Digital Converters”; May 1999; IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing; vol. 46, No. 5; pp. 549-553.
Lewis, Stephen H.; “Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications”; Aug. 1992; IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing; vol. 39, No. 8; pp. 516-523.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

CCD imager analog processor systems and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CCD imager analog processor systems and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CCD imager analog processor systems and methods will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3901311

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.