CCD delay line capable of automatic adjustment of an input bias

Details CCD delay line capable of automatic adjustment of an input bias CCD delay line capable of automatic adjustment of an input bias

1993-03-30

1995-01-10

Mancuso, Joseph

Television

Camera, system and detail

Solid-state image sensor

348300, 348316, 377 58, 377 60, 257238, H04N 5335

Patent

active

053811771

ABSTRACT:
A CCD delay line comprises of first, second and third transfer regions which are formed in a semiconductor substrate. Output portions of the second and third transfer regions are connected to a differential amplifier. The output terminal of the differential amplifier is connected to input sources of the first and second transfer regions. The third transfer region is able to carry at most 30% of maximum amount of charge which the first and second transfer regions can carry. A signal is supplied from a signal source through a clamp circuit to an input gate electrode of the first transfer region. Bias changing means independently change one of an input bias voltage supplied to the input gate electrode of the first transfer region and a reference bias voltage supplied to an input gate electrode of the second transfer region.

REFERENCES:
patent: 4574384 (1986-03-01), Murata et al.
patent: 5029189 (1991-07-01), Sato et al.
patent: 5115155 (1992-05-01), Miida et al.
patent: 5140623 (1992-08-01), Imai et al.
patent: 5177772 (1993-01-01), Narabu et al.
patent: 5210777 (1993-05-01), Narabu et al.
Horowitz & Hill, the Art of Electronics (2nd Edition), p. 8.

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