CCD Correlated quadruple sampling processor

Details CCD Correlated quadruple sampling processor CCD Correlated quadruple sampling processor

1979-02-06

1981-04-14

Dixon, Harold A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307352, 307353, H03K 500, H03K 5159

Patent

active

042622581

ABSTRACT:
A correlated quadruple sampling processor for improved signal-to-noise ratio in the output of a charge-coupled device (CCD) is comprised of: switching means for momentarily clamping a CCD signal line at a first reference level A before a CCD data pulse and then obtaining a first data sample B with respect to the reference A during a CCD data pulse, and storing the positive sample B-A; switching means for momentarily clamping the CCD signal line a second time at the level C during the presence of the CCD data pulse and then obtaining a second data sample D with respect to the reference level C after the CCD data pulse, and storing the negative sample D-C; and means for obtaining the difference between the stored samples +(B-A) and -(D-C), thus increasing the net signal amplitude by a factor of about 2 while the noise would be increased by only a factor of .sqroot.2 since there will be no correlation in the noise between the double samples +(B-A) and -(D-C) effectively added.

REFERENCES:
patent: 3819953 (1974-06-01), Puckette et al.
patent: 3851260 (1974-11-01), Colin
patent: 3991322 (1976-11-01), Bush et al.

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