Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-06-25
2003-05-13
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S108000, C438S118000, C438S121000, C438S125000
Reexamination Certificate
active
06562656
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for creating a cavity down flip chip package.
(2) Description of the Prior Art
The semiconductor industry is known to be very competitive and is therefore constantly driven to improve semiconductor device performance at competitive prices. The objective of improving device performance can realistically only be achieved by reducing device dimensions, which leads to increased device densities. Devices of increased densities must further be combined to form multi-chip packages that contain not only the high-density semiconductor devices but also contain relatively complex means for the interconnection of the devices that are part of the package.
In many of the complex, multi-device packages a substrate, that is typically ceramic or plastic based, is used for the mounting of devices on the surface thereof and for the formation of the interconnect-interface between the devices and the surrounding circuitry. Many different approaches are used for the purpose of interconnecting multiple semiconductor devices, such as Dual-In-Line packages (DIP's), Pin Grid Arrays (PGA's), Plastic Leaded Chip Carriers (PLCC's) and Quad Flat Packages (QFP's). Multi layer structures have further been used to connect physically closely spaced integrated circuits with each other. Using this technique, a single substrate serves as an interconnect medium, multiple chips are connected to the interconnect medium forming a device package with high packaging density and dense chip wiring. The chip wiring contains layers of interconnect metal that are interconnected with interconnect vias, layers of dielectric (such as polyimide) or insulating layers separate metal layers that make up the interconnect network and the via and contact points that establish connections between the interconnect networks. The design of overlying and closely spaced interconnect lines are subject to strict rules of design that are aimed at improving package performance despite the high density packaging that is used. For instance, electrical interference between adjacent lines is minimized or avoided by creating interconnect lines for primary signals that intersect under 90 degree angles. Surface planarity must be maintained throughout the construction of multi-layer chip packages due to requirements of photolithography and package reliability. Many of the patterned layers within a layered structure form the base for overlying layers, lack of planarity can therefore have a multiplying effect on overlying layers.
The Quad Flat Package (QFP) has been created to achieve high pin count integrated packages with various pin configurations. The pin I/O connections for these packages are typically established by closely spaced leads distributed along the four edges of the flat package. This limits the I/O count of the packages and therefore the usefulness of the QFP. The Ball Grid Array (BGA) package has been created whereby the I/O connects for the package are distributed around the periphery of the package and over the complete bottom of the package. The BGA package can therefore support more I/O points and provides a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mil spacings in a regular or staggered pattern.
Where circuit density keeps increasing and device feature size continues to be reduced, the effect of the interconnect metal within the package becomes relatively more important to the package performance. Factors that have a negative impact on circuit performance, such as interconnect line resistance, parasitic capacitance, RC-delay constants, crosstalk and contact resistance have a significant impact on the package design and its limitations. A significant power drop may for instance be introduced along the power and ground buses where the reduction of the interconnect metal does not match the reduction in device features. Low resistance metals (such as copper) are therefore finding wider application in the design of dense semiconductor packages.
Increased I/O combined with increased high requirements for high performance IC's has led to the development of Flip Chip packages. Flip chip technology fabricates bumps (typically Pb/Sn solder) on Al pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger, and to more sophisticated package media that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Temperature Coefficient of Expansion (TCE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
For devices that have high power dissipation, cavity down BGA packages are frequently used. The BGA cavity down package has a structure such that the semiconductor die and the BGA balls both reside on the bottom side of the BGA substrate, that is the side of the BGA substrate that faces the printed wiring board. The structure thereby allows the top-side of the BGA substrate to be available for heat removal purposes.
As an illustration of a Prior Art cavity down package, a method of packaging a BGA is shown in FIG.
1
. The features of this package can be identified as follows:
10
′ is the heatsink of the package, heatsink
10
′ has a surface that is electrically conductive; mounted in the heatsink is
12
′, the semiconductor device; contact points for the die
10
′ are closely spaced around the periphery of the die; the chip
12
′ is interconnected to surrounding circuitry be means of the interface
14
′ which contains one or more layers of interconnect wiring; layer
14
′ can contain a stiffener that provides rigidity to the substrate; contact points that have been provided in the surface of chip
12
′ are connected to substrate
14
′ by means of
16
′, the wire bond connections; the wire bond connections provide a wire bonded connection between a contact points on the IC die
12
′ and the copper traces
19
′ contained in layer
18
′, additional points of electrical contact are provided in the surface of substrate
14
′ by means of points
18
′ which are contact pads to which, typically, contact balls are connected for further mounting of the indicated package; device
12
′ is mounted inside a cavity that has been provided in the surface of the heatsink
14
′ and contacts the heatsink via
layer
20
′, which is a thermally conductive adhesive layer, typically containing epoxy; the device
12
′ is further protected from the environment by being encapsulated in layer
22
′, which forms an epoxy based protective enclosure for device
12
′; the layer
24
′ is the adhesive interface between the substrate
14
and the heatsink
10
′.
The Prior Art package that is shown in
FIG. 1
contains a heat sink in which a cavity is provided for the insertion of a semiconductor die, a substrate that contains one or more layers of interconnect lines and methods of encapsulating the mounted semiconductor
Ackerman Stephen B.
Lebentritt Michael S.
Saile George O.
Thin Film Module, Inc.
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