Cavity-down chip carrier with pad grid array

Details Cavity-down chip carrier with pad grid array Cavity-down chip carrier with pad grid array

1989-05-11

1991-06-25

James, Andrew J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 80, 361386, 361388, H01L 2312, H01L 2302

Patent

active

050271911

ABSTRACT:
The invention is an improved chip carrier assembly utilizing a cavity-down chip carrier with a pad grid array wherein the IC chip within the chip carrier is mounted against a surface opposite the PWB to which the chip carrier is attached such that heat transfer from the IC chip may occur along a short path to a heat sink such that a large heat transfer rate is possible. Furthermore, the apparatus utilizes an alignment and electrical connection means between the contact pads of the chip carrier and a PWB to which the chip carrier is attached to compensate for shrinkage variation which occurs during the chip carrier fabrication process. Furthermore, within the cavity of the chip carrier there is space for additional components such as a decoupling capacitors. This permits the design of an apparatus providing better heat transfer properties, more accurate contact pad locations and the option of including within the chip carrier components which in the past had been mounted outside of the chip carrier.

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European Patent Application, Publication Number 0150928-A2 Published 8/7/85 entitled, "A Compliant Interconnection Device and Assembly Method of Manufacture, and of Micro Interconnection Casting."
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