Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2003-01-14
2004-11-16
Thompson, Gregory D. (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C165S080200, C165S080300, C165S185000, C257S707000, C257S713000, C257S738000, C257S778000, C257S774000, C361S707000, C361S708000, C361S717000, C361S718000, C361S722000
Reexamination Certificate
active
06819565
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader.
BACKGROUND OF THE INVENTION
A ball grid array (BGA) semiconductor package adopts advanced packaging technology, characterized in the use of a substrate with at least a semiconductor chip being mounted on a surface thereof and a plurality of array-arranged solder balls being implanted on an opposing surface of the substrate, so as to allow more input/output (I/O) connections (e.g. solder balls) to be implanted on a chip carrier (e.g. substrate) in response to high integration of the chip, to thereby electrically connect the semiconductor package to an external printed circuit board (PCB) by means of the solder balls.
U.S. Pat. No. 5,545,923 discloses a semiconductor package with a ground ring, a power ring and a plurality of signal fingers being formed on a substrate. As shown in
FIG. 1
a
, in this semiconductor package
1
, the ground ring
113
, power ring
114
and signal fingers
115
are disposed at area other than a chip attach region
110
on a first surface
111
of the substrate
11
. A semiconductor chip
12
having a plurality of ground pads, power pads and signal pads (not shown) is mounted on the chip attach region
110
. A wire-bonding process is performed to form a plurality of ground wires
133
, power wires
134
and signal wires
135
, wherein the ground wires
133
electrically connect the ground pads of the semiconductor chip
12
to the ground ring
13
of the substrate
11
, the power wires
134
electrically connect the power pads of the semiconductor chip
12
to the power ring
114
of the substrate
11
, and the signal wires
135
electrically connect the signal pads of the semiconductor chip
12
to the signal fingers
115
of the substrate
11
. Then, a plurality of solder balls
14
are implanted on a second surface
112
of the substrate
11
, and electrically connected to the corresponding ground ring
113
, power ring
114
and signal fingers
115
respectively via conductive traces (not shown) formed on the second surface
112
of the substrate
11
. By electrically connecting the semiconductor package
1
to an external device via the solder balls
14
, the ground ring
113
and power ring
114
help maintain electrical quality of the semiconductor package
1
, and provide grounding effect and power supply as required for operation of the semiconductor chip
12
.
However, due to dense arrangement of electronic elements and circuits on the highly integrated semiconductor chip, a large amount of heat is produced during operation; if the heat can not be effectively dissipated, it would seriously damage performance and lifetime of the semiconductor chip. Moreover, this package structure lacks sufficient shielding effect, and thereby is easily subject to external electromagnetic and noise interference.
In order to solve the foregoing problems, U.S. Pat. No. 6,020,637 discloses a cavity-down ball grid array (CDBGA) semiconductor package; as shown in
FIG. 1
b
, this semiconductor package
2
comprises: a tape substrate
22
, a heat spreader
200
, a ground plane
202
, at least a semiconductor chip
23
, a plurality of bonding wires
24
, an encapsulant
25
and a ball grid array
260
.
The above semiconductor package
2
utilizes a two-layer heat sink
20
composed of the heat spreader
200
, an adhesive layer
201
and the ground plane
202
, wherein the ground plane
202
is formed with an opening
2020
for chip accommodation, and a ground ring
21
is disposed around the opening
2020
. The substrate
22
is attached to the ground plane
202
, and formed with a plurality of vias
220
. The semiconductor chip
23
is mounted to the heat spreader
200
by means of the adhesive layer
201
and received within the opening
2020
; this semiconductor chip
23
is electrically connected to the ground ring
21
by a plurality of first bonding wires
240
a
, and electrically connected to conductive traces (not shown) formed on the substrate
22
by a plurality of second bonding wires
240
b
, allowing the semiconductor chip
23
and bonding wires
240
a
,
240
b
to be encapsulated by the encapsulant
25
. And, a plurality of solder balls
260
a
,
260
b
are implanted on the substrate
22
, wherein the solder balls
260
a
are connected to the vias
220
of the substrate
22
for allowing the heat sink
20
to be electrically connected to a printed circuit board (PCB, not shown) by the vias
220
and solder balls
260
a
(ground balls).
Although the above semiconductor package
2
provides solutions to the problems of heat dissipation and electromagnetic interference, it requires complex fabrication processes and high costs; further, voids may be easily formed in the vias
220
during fabrication, thereby degrading electrical connection between the ground balls
260
a
and the ground plane
202
.
Furthermore, the ground ring
21
of the ground plane
202
used in the above semiconductor package
2
is also made by complex processes. First, the ground ring
21
is formed by plating gold (Au) or silver (Ag) over the ground plane
202
; then, a black oxidation process is performed at area other than the ground ring
21
on the ground plane
202
, allowing the ground plane
202
to have good adhesion to the tape substrate
22
. However, the black oxidation process would easily contaminate the pre-formed ground ring
21
, and thus degrade bondability of the first bonding wires
240
a
and adherence between the ground ring
21
and the encapsulant
25
, thereby adversely affecting quality and reliability of fabricated products.
Therefore, the problem to be solved herein is to provide a semiconductor package, which can simplify fabrication processes, reduce costs, and solve the problems of heat dissipation, electromagnetic interference and crosstalk effect.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader, wherein a substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is applied between an inner wall of the cavity and edges of the substrate, whereby the heat spreader can be electrically connected to a metal ground layer exposed to the edges of the substrate by means of the electrically conductive adhesive, so as to simplify fabrication processes, reduce costs, and solve problems of heat dissipation, electromagnetic interference and crosstalk effect.
In accordance with the above and other objectives, the present invention proposes a CDBGA semiconductor package with a heat spreader, comprising: a substrate having a first surface and a second surface, and formed with an opening, a metal ground layer exposed to edges of the substrate, at least a ground ring formed at peripheral area on the second surface of the substrate, and a plurality of ground vias; a heat spreader formed with at least a cavity, allowing the substrate to be mounted in the cavity with the first surface of the substrate being attached to the heat spreader; a semiconductor chip having a circuit surface and a non-circuit surface, and mounted in the opening of the substrate with the non-circuit surface of the semiconductor chip being attached to the heat spreader; an electrically conductive adhesive for connecting the exposed metal ground layer and the ground ring of the substrate to an inner wall of the cavity of the heat spreader, allowing the ground layer and ground ring to be electrically coupled to the heat spreader by the electrically conductive adhesive; a plurality of bonding wires for electrically connecting the semiconductor chip to the substrate; an encapsulant for encapsulating the semiconductor chip and bonding wires; and a plurality of solder balls implanted on the second surface of the substrate, for electrically connecting the semiconductor chip to an external device
The above CDBGA semiconductor package according to the invention is charact
Chiang Wen-Jung
Kao Nai-Hao
Wang Yu-Po
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
Thompson Gregory D.
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