Causality based event driven timing analysis engine

Details Causality based event driven timing analysis engine Causality based event driven timing analysis engine

2007-07-03

2007-07-03

Paladini, Albert W. (Department: 2125)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C702S079000

Reexamination Certificate

active

10447762

ABSTRACT:
Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.

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