Chemistry: electrical and wave energy – Apparatus – Coating – forming or etching by sputtering
Reexamination Certificate
1999-10-14
2001-07-24
Nguyen, Nam (Department: 1753)
Chemistry: electrical and wave energy
Apparatus
Coating, forming or etching by sputtering
Reexamination Certificate
active
06264813
ABSTRACT:
TECHNICAL FIELD
This invention relates to cathodic sputtering targets designed for metallization of various substrates. It particularly relates to targets designed for the manufacture of integrated circuits, particularly for the manufacture of interconnection circuits, and for metallization of large flat panel displays (FPD).
The invention relates particularly to aluminum alloys used for the active part of cathodic sputtering targets.
In this application, the contents of elements and impurities are expressed in values by weight.
STATE OF PRIOR ART AND PROBLEMS
The electronics industry uses large quantities of electrical interconnection circuits based on aluminum or aluminum alloys, particularly in very high level integration circuits such as DRAM dynamic memories with a capacity exceeding 4 Megabits, and flat panel displays (FPD) such as liquid crystal displays (LCD) and particularly displays controlled by thin film transistors (TFT).
These interconnection circuits are obtained industrially using the well known technique of cathodic sputtering, which is capable of depositing different types of refractory or non-refractory, alloyed or unalloyed, conducting or dielectric materials, on different types of substrates that may be put under a vacuum and that can resist a small temperature rise. Known procedures generally include a series of substrate metallization, etching and passivation operations on the metallic layer. During metallization, the substrate is generally kept at a temperature, called the metallization temperature (Tm) exceeding 180° C., and usually of the order of 200° C. to 250° C., although the current trend is to use metallization temperatures of the order of 170° C. to 200° C.
In very high level integration circuits, the metallic layer is typically 0.5 &mgr;m to 1 &mgr;m thick, the etching is very thin (typically of the order of 0.25 to 0.5 &mgr;m) and current densities are very high, sometimes as high as 10
6
A/cm
2
, particularly during accelerated aging tests. Under these conditions, a degradation of circuits is observed during use due to an electromigration phenomenon that causes the formation of holes and protrusions. A well known way of solving this problem is to do the metallization using aluminum alloys with high contents (usually greater than 2500 ppm) of chosen added alloying elements (additives) such as Cu, Ti, Si., Sc, Pd and combinations of these elements. However, these alloys have the disadvantage that etching is fairly difficult, particularly due to the different reactivity of aluminum and additives to reagents used for etching the circuits, and the sometimes difficult removal of products derived from chemical etching reactions, particularly for dry etching processes.
Japanese patent applications JP 62.235451 to JP 62.235454 and JP 62.240733 to JP 62.240739 also describe the use of high purity aluminum alloys containing limited additions (usually less than 200 ppm) of copper, cobalt, manganese, nickel, tin, indium, gold or silver together with additions of refractory metals such as titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum or tungsten in quantities between 20 and 7000 ppm and additions of boron, carbon, and/or nitrogen in quantities of between 20 and 5000 ppm. These complex alloys have the disadvantage that they are difficult to make, and particularly that they flow without local segregations of inter-metallic elements, which can cause heterogeneity of the target composition.
However in the case of flat panel displays, the width of etchings is usually greater than or equal to 10 &mgr;m, and the use of widths of the order of 5 &mgr;m is considered in order to improve the image definition. Therefore, etchings of flat panel displays are much less fine than etchings of very high level integration circuits. Current densities are also significantly lower. Under these conditions, deterioration of circuits by electromigration is practically non-existent, such that the use of alloys with high contents of additives is no longer justified. Therefore, it is usually preferred to use very pure unalloyed aluminum which has the important advantage that it is much more easily etched than alloys, and that it has a very high electrical conductivity and good resistance to corrosion.
The current trend in the field of flat panel displays, which is developing very quickly, is the production of large displays. Current developments are aimed particularly at PC monitors with diagonals measuring 17″ and 20″, and flat wall television screens with 40″ diagonal, in other words surface areas of up to about 0.5 m
2
. Furthermore, for productivity and efficiency reasons, these monitors and screens are obtained either directly or by cutting from the same substrates (also called “glasses”). Consequently, the current trend is a fast increase in the size of glass substrates. The current standard formats are about 360 mm×460 mm, and will soon be increased to 550 mm×650 mm, and the use of substrates of about 800 mm×1000 mm is being considered for simultaneous production of 17″, 20″ and 40″ diagonal flat panels.
These trends have rendered preponderant the problem of the appearance of “voids” and “hillocks” at the surface of metallization films during heat treatments inherent to monitor manufacturing processes, making the films unusable more and more frequently as the display size increases. In particular, this is the case for displays manufacturing processes that include the formation of thermal oxide films by heating to temperatures exceeding 300° C. or the deposition of complementary layers by chemical vapor deposition (CVD). The voids and hillocks produced by this type of heat treatment can cause interconnection faults that degrade the image quality. Since the image quality criteria are severe, only a few faults are necessary to make it necessary to scrap a complete monitor during production.
The cause of this problem is not well understood. According to one explanation put forward (P. R. Besser et al, Materials Research Society, Symposium Proceedings, Vol. 309, 1993, p. 181-186 and 287-292), and which is generally accepted, the appearance of hillocks and voids is particularly due to the appearance of very severe constraints caused by the large difference in the coefficient of thermal expansion between the aluminum film and the substrate. These stresses could significantly exceed the yield strength of aluminum. When the monitor temperature is increased above the metallization temperature, the aluminum film would be put into compression and some grains (the more plastic) would be extruded outside the film under the pressure of the adjacent grains. During cooling, the film would be tensioned and holes would appear thus relaxing the stresses (phenomenon referred to as stress voiding). According to some authors, the appearance of hillocks is related to the existence of areas with grains with a different orientation than the rest of the film when the film has a strong structure (D. B. Knorr, Materials Research Society, Symposium Proceedings, Vol. 309, 1993, p. 75-86). Finally, other authors associate the formation of hillocks with a phenomenon of abnormal growth of some grains due to the existence of some joints with a particular orientation and with a very high mobility (K. Rajan, Electrochemical Society Proceedings, Vol. 95-3, 1995, p 81-93).
It is proposed to solve this problem, particularly in the field of integrated semiconductor circuits, by using multi-layer interconnection circuits, in other words formed of alternate thin layers of aluminum alloys and refractory metals. For example, the American patent U.S. Pat. No. 4,673,623 recommends the use of several alternate layers of aluminum alloy (Al+1% Si) and titanium or tungsten. According to European patent application No. 681 328 by Xerox Corp., the thickness of each alternate layer is preferably limited to a small value less than a critical value at which the hillocks occur. U.S. Pat. No. 5,171,642 to IBM Corp. proposes the use of alte
Chenal Bruno
Leroy Michel
Muller Jean
Aluminum Pechiney
Cantelmo Gregg
Connolly Bove & Lodge & Hutz LLP
Nguyen Nam
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